Category: Hardware
Product Number: AD9173
Hello,
We have designed hardware using the AD9173 DAC, and we are currently verifying its output using a spectrum analyzer.
We generated a DC tone and measured the output power at different signal levels. The DAC data and corresponding output levels are as follows:
| DAC Data (I/Q) | Input Level | Measured Output (dBm) |
|---|---|---|
| I:-464 / Q:926 | -30 dBFS | -37.43 dBm |
| I:-146 / Q:292 | -40 dBFS | -44.89 dBm |
| I: -46 / Q:92 | -50 dBFS | -50.21 dBm |
| I: -14 / Q:29 | -60 dBFS | -52.82 dBm |
| I: -4 / Q:9 | -70 dBFS | -53.84 dBm |
| I: -1 / Q:2 | -80 dBFS | -54.72 dBm |
| I: 0 / Q:0 | zero | -100.00 dBm (noise floor) |
We expected the output power to decrease linearly with a 10 dB step in the digital input level. However, starting from -50 dBFS, the output power reduction becomes significantly smaller than expected.
Question:
What could be the cause of the limited output level reduction below -50 dBFS?
Is there a known floor in the AD9173 digital-to-analog conversion path, or could this be related to the analog output stage or measurement setup?
Any insight or advice would be appreciated.
Thank you.
