Hi,
I am tring to synchronize multichip to generate two fixed phase difference signal. When two DACs are outputting signals in a stable sence, the phase difference stay stable; but when changing the value of FTW for around 4 times, the phase difference between two signals change.
I am following the description of synchronization procedure for PLL off in the AD9142A datasheet. Here is my configuration of register:
reg input setting
0x28 0x02
0x31 FTW[7:0]
0x32 FTW[15:8]
0x33 FTW[23:16]
0x34 FTW[16:24]
0x30 0x11
0x25 0x01
0x42 0x41
0x27 0x50
0x22 0x0a
0x21 0x03
According to the description of the datasheet, the I can get a high value from 0x22[3], but the feedback information is different to the description. Here is the feedback information:
reg reading back value
0x30 0x33
0x22 0x01
0x21 0x03
I wonder if my setting is right, or getting some suggestions of synchonizing multichip. I am grateful for suggestions and disscussion. Thank you!