Problem of doing multichip synchronization

Hi A11en ,

Thank you for your interest in AD9142A. Your query is acknowledged and will be responded to by the product owner soon.

Regards,
Zaeefa

Hi A11en ,

Thank you for your interest in AD9142A. The DLL should be enabled and locked as per the synchronization procedure. Were you able to verify if the DLL is locked? This can be enabled in Register 0x0A and verify it's locked in Register 0x0E. 

Also, since you will synchronize the NCO output from multiple devices, the frame-initiated update is recommended instead of the SPI initiated update as prescribed in Page 34 of the Rev B datasheet. In the Synchronization procedure for PLL Off described in Page 38, there's a bit of typo: Step 8 is supposed to be verify that Register 0x30[6] should read back 1 instead of Register 0x22[3] to verify that there's a complete Frame-initiated NCO FTW update. 

Best regards,
Marco

Hi Marco,

Thank you for your reply. After I double checked the configration, I find that the the setting of the Register 0x0D to  0x16, and set the Register 0x0A to 0x0 to disable the DLL. 

I set the DCI rate to 160MHz, which is not exceed 250MHz. So I follow the recommendation in Register 0x0D, disabled the DLL and enabled the delay line. Is it mandatory to enable the DLL for the synchronization, even if the DCI rate does not fast enough?

Moreover, I want to know more about the relationship between the DLL and the synchronization. When looking at the functional block diagram, I notice that the DLL is working to the DCI directly, and the FTW is updated base on the DAC_CLK. Is theree any mutual influence between them?

I am looking forward to your reply, thank you very much.

Best regards,

Allen