Hi,
the manual of the AD9122 Evaluation Board states that "A sinusoidal clock output level of 0 to 4dBm is optimal". This refers to the Clk-input pins of the AD9516, which are connected via a balun to the SMA-port J1:
If I want to use a DACClk of 800MHz, I primarily would have to apply an 800 MHz sine wave input on J1. But I only have a CMOS Clock signal available. Due to the Balun and its poor performance above 1 GHz (https://cdn.macom.com/datasheets/MABACT0043.pdf), I am not sure if it is a good idea to apply it on J1. I am using a custom controller board for the AD9122 Evaluation Board. My questions are:
1.) Would you recommend applying a 800MHz square wave input on J1 (Clk-input)? I guess it would also be possible to provide a lower frequency signal and then use the PLL to generate 800MHz at the outputs.
2.) Or is it better to apply the square wave on J14 (RefCKp) instead and not use J1 entirely? Even with a slower frequency to generate 800MHz via the internal PLL?
I know that Nr. 2 would result in a slightly worse Jitter performance, but this is OK in my case.
Thank you very much!
