AD9164: Disable unused lanes

Hi john82 ,

Your inquiry has been acknowledged. Kindly allow a few days for the product owner (MohammedHossain) to review the matter and provide a response.

Thanks and kind regards,

Alex

Any unused and enabled lanes consume extra power unnecessarily. Each lane that is not being used (SERDINx±) must be powered off by writing a 1 to the corresponding bit of PHY_PD (Register 0x201).

Yes, I’m aware of that. I would like to remain in mode L=8 M=1 F=1 and S=4, but disable lanes 1, 3, 5, and 7. The converter should interpret the missing LSBs with a constant value (or from an existing lane).

For testing purposes, I’ve already disabled the lanes in register 0x201 and routed lane 0 to lane 1, lane 2 to lane 3, and so on in the cross-matrix.

This worked successfully in the test, and I’m getting a usable signal.

The problem now is that when I disable the lanes in the FPGA, the complete synchronization on the K-symbols fails on all lanes. Could it be that the CDR fails on the now-disabled lanes, causing the synchronization process to break down? Is it possible to disable the CDR on the inactive lanes?

 MohammedHossain
Any ideas?