JESD link down on AD9164

Hi,

My design use AD9164+KU060+HMC7044 architecture, Fdac = 2.4G, LMFS=8114, HMC7044 distributes clk/sysref to FPGA(150M+4.6875M)/DAC(2.4G+4.6875M) respectively. (GTH ref clk use local 100M SPXO)

Actually, designing with AD9164 has similar frame in the previous 2 projects, but i got new problem in this project. I already went through most posts and tried several days, but made few progress.

Issue as per title: JESD link down soon after link up. as below capture, the syncb starts toggling(for 1 clk pulse) while link goes to user data phase. and finally with a long low pulse and tready goes down.

more info:

the register configuration as below:

addr   data
0       99
0       18
200     1
d2      52
d2      d2
606     2
607     0
604     1
(rd 604= 42)
58      3
90      1e
80      0
40      0
20      f
9e      85
91      e9
(rd 92= 1)
e8      20
152     0
300     0
4b8     ff
4b9     1
480     38
481     38
482     38
483     38
484     38
485     38
486     38
487     38
110     80
111     0
230     8
289     1
84      0
200     0
475     9
452     1
453     7
455     1f
458     2F
459     2F
47D     0
45D     4A
475     1
201     0
2A7     1
2AE     1
29E     1F
206     0
206     1
280     3
(rd 281= B)
300     1
24      1F
4BA     FF
4BB     1

actually I found some abnormal values:

1, error report caused by BDE, NIT,UEK.(0x46D-0x46E are 0xFF, 0x46F changes by re-cycle power on)

2, failed to pass checksum.(0x470/471/473 are 0xFF but 0x472=0)

Could you help to on:

1, how to handle the  BDE, NIT,UEK error?

2, any suggestion on the checksum failure? (i read out the 0x400-0x40D, which are exactly matching the 0x450-0x45D).

Thanks a lot!