Waveform distortion of the output signal using DAC

Question

DDS is used to generate sine waves for output. The AD9142A is controlled by FPGA. The DAC outputs sine waves as well. This phenomenon occurs for all frequencies ranging from 1Hz to 1MHz. It can be observed on the oscilloscope that there is a segmented phenomenon. Every four segments have a step, like steps, and always opposite to the general direction. When the sine wave value increases, the steps are downward, presenting a four-segment downward step shape. When the sine wave value increases, the steps are upward, presenting a four-segment upward waveform. Below 2MHz, the waveform clock has steps, while above 10MHz it is smoother. However, at high frequencies, I noticed from the modelsim simulation that only 8 points are output.

AlexAtienza · Accepted Answer

Hi PerSTAR 
 
 For SCLK if requires and external pull-up or pull-down
 
 Since AD9142A uses CMOS signaling, external resistors might be necessary to ensure correct voltage levels or reduce noise.

For strange IRQ signal
 
 You can check for possible timing issues that result to DAC clock not met. Instability in the clock signals can lead to inconsistent IRQ behavior. Kindly inspect the physical connections (loose or faulty) including SPI interface and clock lines.

Thanks and kind regards, 
 Alex)

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Waveform distortion of the output signal using DAC