Waveform distortion of the output signal using DAC

Hi PerSTAR ,

Thank you for your interest in AD9142A. Kindly give us a few days to inspect this issue and we'll get back to you. Are you using the AD9142A Eval Board? If not, can you provide your schematic, register configuration, and target application? Also what modelsim simulation are you referring to? 

Best regards,
Marco

I did not use the AD9142AEVM. Instead, I utilized the MODELSIM simulation jointly with Zi Guang Tong Chuang, and employed MATLAB to generate 8192 sine wave data as the ROM table. Then, I used DDS to output sine waves.Convert 16-bit data into differential data and assign them to Q and I respectively. Then output these data in parallel. I have a question: Is this serial or parallel operation?PDFMy schematic diagram is quite similar to this one .

And this is the waveform of the IRQ signal at pin 51.

CVDD18:1V9   DVDD18:1V8  

Hi PerSTAR ,

Is this MODELSIM simulation provided by ADI? Unfortunately, we do not provide support on the code you developed. I would suggest checking these captures in the frequency domain using a spectrum analyzer to inspect what frequencies show at the output. I also suggest performing the relevant debugging steps such as checking the power supplies (at the DAC pins) if they are within specs, check the quality of the clock input signal, and check the FIFO lanes if there are any warnings.

To answer your question: AD9142A has an LVDS architecture thus the digital inputs should be parallel operation.

Best regards,
Marco 

Hi  Marco，

The clock frequencies of DCI and REFCLK are both 80 MHz.The speed of FPGA data update is also 80 MHz. Could you please check the register configuration for me, or provide a configuration file? I'll try again. If the clock is not aligned, can we adjust the DLL? The register address is 0x0A.Could you please check for me if the interpolation configuration is correct?Looking forward to your reply.

Warm Regards，

PerSTAR 

Hi JMMina

And this one

Hi PerSTAR ,

Apologies for the delay. Can you provide your full register map and DAC settings (DAC clock, interpolation, Data Bus Width, etc.) so we can try to replicate it on bench using the AD9142A Evaluation Board? Alternatively, you can try out the sample start-up sequence provided in page 47-48 of the Rev A datasheet. 

The DLL is designed to operate between clock rates of 250 and 575 MHz so I'm afraid it's not recommended to use in your case. What do you mean 'REFCLK'? Are you using the DAC PLL to generate the internal clock for the DAC? 

Best regards,
Marco

Hi JMMina

IRQ signal is strange.Could you explain the reason for me?

Best wishs,

PerSTAR