power up sequence timing requirement

Question

In the datasheet it's described: "The IOVDD, VDD12A, VDD12_CLK, and DVDD domains must be powered up first. Then, the VNEG_N1P2, VDD_1P2, PLL_CLK_VDD12, DVDD_1P2, and SYNC_VDD_3P3 can be powered up. The VDD25_DAC domain must be powered up last." 
 Are there any delay time requirement between these power domains? 
 For example, after IOVDD, VDD12A, VDD12_CLK, and DVDD domains powered up, how long time should we wait before "the VNEG_N1P2, VDD_1P2, PLL_CLK_VDD12, DVDD_1P2, and SYNC_VDD_3P3 powered up"? Is it okay if it's as short as 500us?

zpandangan · Accepted Answer

Hi howardaaa , 
 Thank you for your interest in AD9163. 
 There is no specific delay time requirement between the power domains. However, the interval between powering them up should be enough such that the rails are stable at their levels prior to turning on the others in succession. In the AD916x evaluation board for example, a ~380-ms delay is applied before the rails that are next in order are enabled. 
 Regards, Zaeefa)

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power up sequence timing requirement