Hello,
I am working with the AD9767 DAC in Dual-Port Mode using an evaluation board with FPGA integration, and I have encountered an issue. The presence of additional spurious signals in the spectrum of the DAC output is observed depending on the complexity of the FPGA project. However, when I switched to using an external clock source, this issue was resolved.
In my custom design, I intend to use an external clock that is isolated from the FPGA clock, but I am uncertain about how to correctly interface the external clock with both the DAC and FPGA without violating the timing requirements as outlined in the datasheet.
Could you please provide guidance on how to properly implement the external clock for the AD9767 while ensuring the integrity of the timing diagram? I have included my current schematic below for reference.
Thank you.
