ad9783 configuration and noise floor

Hi AnishC ,

Thank you for using AD9783. Please give us a brief period to look into this and provide you with a response.

Regards,
Zaeefa

ok sir

Hello,

To ensure proper sampling of the input data (DATA), one must ensure that the data sampling clock, DSS, does not sample the input data during its transition region highlighted in yellow below.   Note that sampling of data occurs on both rising and falling edge hence the reason that the DCIP/DCIN is generated as an extra data bit that alternates as a 010... pattern such that its transitions are aligned perfectly with that of the DATA. 

The procedure outlined in datasheet to set the DSS delay such that it avoids these transition regions with added margin.  Note that the ideal sampling instance of DATA is at the midpoint where the set-up  and hold time are near equal so that any +/- drift delay of DSS (due to ambient temperature changes) will not result in DSS to sample DATA on these transitions.  It is also worth noting that the DATA transition region is likely to be around 200-300 psec range depending on the LVDS driver hence this "keep-out-window" (KOW) represents a higher percentage of the data rate at 500 MSPS  (12-15% for data period of 2 nsec) vs 50 MSPS  (i.e. 1.2 to 1.5% for data period of 20 nsec).  So......for your use case of 63.87 MSPS (15.65 nsec data period), simply setting the SMP_DLY to its max value of 15 resulting in a delay of approximately 2.7 nsec should provide sufficient margin.............albeit one should still go through the time optimization procedure outlined in datasheet.

Thank you sir.
I will follow your suggestion and get back to you with the results.
My goal is to achieve an SFDR of 70 dBc, as required for our application, but so far I have only been able to reach around 60 dBc.

It is worth noting that when a timing violation does occur, it is quite evident on a spectrum analyzer since a clean spectrum consisting of the desired sine wave output (used for testing DAC signal purity) and associated low level harmonics will be become heavily distorted with high noise floor/spurious since the digital sine wave is no longer being faithfully recreated.

Perhaps you can post a spectral plot of the DAC output with spectrum analyzer showing 1KHz to FDAC rate on display.

ok sir
I shall get back to you with the results.

Hi sir...
Extremely sorry for being late in reply as we were stuffed with the delivery of other projects. As per our last discussion, I hereby share the spectral plot of the DAC output with a span of 1KHz to FDAC rate[400MHz]. The input to the DAC is given from a DDS that generate sine wave samples of 63.87MHz.

I have one more doubt sir, we calculated SFDR by taking the difference (in dBm) between the CF peak and its associated highest harmonic [here the second one]. Could you please confirm whether our measurement approach is correct?

Thanking you

AnishC

Hello,

Looking at the spectral plot, it would appear that the 63.87 MHz with power level at 7.6 dBm is much higher than expected if the DAC was driving a ground referenced transformer or balun that provides a DC biased path to AGND.

Could you copy/paste the portion of schematic for DAC including output interface to next stage components to understand source of distortion and high output power.