


AD9523-1
Recommended for New Designs
The AD9523-1 provides a low power, multi-output, clock distribution function with low jitter performance, along with an on-chip PLL and VCO with two VCO...
Datasheet
AD9523-1 on Analog.com
AD9125
Recommended for New Designs
The AD9125 is a dual, 16-bit, high dynamic range TxDAC+® digital-to-analog converter (DAC) that provides a sample rate of 1000 MSPS, permitting a multicarrier...
Datasheet
AD9125 on Analog.com
The dac output is connected to an IQ modulator via passive filter. The IQ modulator input command voltage is 1.7V. I'm wondering is this problem caused by the common-mode voltage not being matched?
Hi w.yue ,
Thank you for using AD9125. We'll look into this and get back to you with a response as soon as possible.
Regards,
Zaeefa
Hello,
The main cause of not seeing a signal at its output is that the common-mode voltage far exceeds the capabilities of the DAC output whose output compliance range is +-1 V. The current output DAC is meant to source current into a ground referenced load via transformer/balun to get the best AC performance albeit it can still work well with DC coupled interfaces where the common-mode voltage is 0.5 V to support 2 Vpp output or 0.75 V to support 1 Vpp differential output thus keeping peak voltage below 1 V. Plot below shows how DAC AC performance degrades quickly as common-mode voltage increases for different IOUTFS setting due to onset of DAC output compression/saturation.
In your circuit......I suspect that the DC common-mode voltage measured at output well exceeds 0.75 V causing the DAC's output into saturation thus resulting in low signal level. QMODS designed for lower common-mode voltages such as the ADL5385 (ADL5385 (Rev. D) would be a better choice since they are designed for the lower common-mode voltages required by DAC outputs that source current into ground as shown in schematic below showing AD9777 DAC.
Note that the 500 KHz output tone observed in your spectrum analyzer display is a result of the DAC's quad-switch architecture that caused DAC switching on both the + and - clock edges resulting a clock spur that is 2x the DAC update rate.
Hi w.yue ,
We tried to duplicate your concern regarding 500MHz output upon powering up the chip only.
To confirm our results, please help to try to output 10MHz and share the results.
Make your settings as per below:
Start Frequency: 0 Hz
Stop Frequency: 2 GHz
RBW: 30 kHz
On your initial plots, please help to lower the RBW as well to see if there are other visible harmonics.
Thanks and kind regards,
Alex
I'm sorry to reply to your message so late. I found that it is mentioned in CN-0205 that it can be used to level-shift to 1.5v.
Could this level-shifting work for 1.7V using below condition?
Thanks and kind regards,
W.yue
Hi Alex,
I'm sorry to reply so late.
The chip is connected to the modulator device on board, I'm not sure is the results of such a test will meet your requirements.
The Image below shows the dac outpou 0MHz. The Modulator is 1560MHz.
Thanks and kind regards,
W.Yue
Hello,
This is not a valid test since the DAC is only presenting a DC voltage to the modulator input.
One should have the DAC generate a 100 MHz complex sine wave for the modulator input so that one can clearly see the Single-Sideband image, LO feedthrough, and DAC/Modulator induced harmonics when one "zooms" into region of +/-500 MHz centered about the LO frequency.
One last point...................while the dc level shifting approach is valid to shift common-mode from 0.5 V to 1.5 V, it comes at the expense of dynamic range loss due to the lower input signal drive into the modulator (i.e. 0.34 Vp-p vs 1 Vp-p)..............which results in 9.4 dB less signal power at modulator output. Increasing R2 value to accommodate 1.7 V common-mode will further increase power loss.
If a board redesign is required to support the DC level-shifting network in CN-0205 than perhaps the better approach would be to select a modulator that can support 0.5 V common-mode hence achieving the highest dynamic range possible with the simplest interface circuitry.
Hi,
I tried use the dc level shifting to shift common-mode from 0.5v to 1.5v, it doesn't work, still have a 500MHz signal! I'm so confused。
I checked the wave in point A.1 is the IOUT1_N, 2 is IOUT1_P.
And I tyied the DAC output a 10MHz signal(the filter designed is lower then 30MHz), Lo is 1575.5MHz, the results are below.
How shold I solve this problem?
Thanks.
Hello,
The DC level shift "appears" to be working since the 10 MHz sine waves measured at "A" seem to be centered upon 0.5 V. One can also confirm at "B" that the 10 MHz sinewaves are centered about 1.5 V .
With regard to spectral plot, it does appears to be a single-sideband (SSB)output signal with the FUND power being 7.64 dBm; the quad modulators LO feedthrough being rather high at 1 dBm and the "image" being also rather high at -19 dBm. Improvement in the LO feedthrough can be achieved by adding a calibrated DC offset to the I and Q data while the "image" can be improved by modifying the gain of the Q channel to the I channel. Phase imbalance between the I and Q baseband channels and internal modulators LO phase shift of 90 degrees will also contribute to the "image" level but this is more difficult to compensate over a wide frequency span without addition of digital complex equalization filters. Please refer to this application note. AN-1039: Correcting Imperfections in IQ Modulators to Improve RF Signal Fidelity | Analog Devices
As mentioned earlier, the 500 MHz fixed tone that is observed out of DAC output operating at 250 MSPS is due to the quad switch DAC architecture where both rising and falling edges are used in its operation. To reduce this common-mode clock..........best to make the LC filters capacitors shown below also implemented for common-mode rejection by splitting the differential capacitor into two capacitors at 2x the value with each capacitor connected to AGND .................hence providing a low impedance path to ground for this 500 MHz signal.