Hi,
I’m using AD9162 RF DAC with Xilinx Zynq Ultrascale+ and Kintex Ultrasace FPGAs and I have question about bit inversion of AD9162. I’m using AD9162-FMC-EBZ board and I also have a custom board for AD9162. I generated my FPGA project from AD HDL Reference Design “dac_fmc_ebz” which is configured for 8 JESD204B Lanes. Then, I run start up sequence as shown in datasheet Table 42-43-44. During start up sequence, I check JESD sync status from registers 0x470 to 0x473. When I’m using AD9162-FMC-EBZ with Zynq Ultrascale+ FPGA, I get 0xFF from all status registers and I don’t have any problem about JESD link. But when I change FPGA with Kintex Ultrascale, I get 0x00 from Checksum status (Register 0x472). After I apply bit inversion from register 0x334, it is solved and JESD link works fine. I know that P/N pairs are not switched on my Kintex Ultrascale hardware.
In addition to that test, I also run the same test with my custom AD9162 board by using the same Zynq Ultrascale+ hardware. There is also a conflict in that test. When I’m using my custom AD9162 board, only 3 of 8 lanes are passed from checksum and link is not working without bit inversion. But when I apply bit inversion for 5 lanes, I also get 0xFF from checksum and JESD link works fine. I’m sure that P/N pairs are connected right for all of the boards. What could be the reason for this problem? I can work properly when I apply correct bit inversion on these boards, but I couldn’t find the main reason of this problem. Is this any reason for that conflict?
Thanks,
