AD9744 output

Hello,

Boards are tested before being placed into stock hence unlikely issue is due to poor soldering joint or short between pins.

It would seem that the DC blocking capacitors are required (vs 0 ohm shorts) when using the balun path since the balun provides a DC bias to AGND.

Replace these resistor as shown below with 0.1 uF cap and see if problem is resolved.

Hello PMH2023,

Thank you for your response.

After modification, we tested the DAC with various sampling frequencies and input signals and observed the output on DSO, I couldn't get a nice sine wave. I've provided a snapshot below for
(a)25MHz sampling frequency from signal generator and 2.5MHz & 1MHz input signals generated using the Xilinx DDS compiler IP.
(b)Increased the sampling frequency to 200MHz by continuously inputting four samples (0,8192,0,-8192) (VHDL logic).

2) Is there an HDL project (non-OS driver) for testing the AD9744 evaluation board with the internal clock?

 a.1

a.2

 b.1 ILA

b.2 

It looks like the DAC is now working fine.  When you sample at 25 MSPS, one can easily see the DAC produce closer to its ideal stair-case waveform where it transitions between different samples and holds the level until the loading the next sample.   The reason that it is not infinitely "sharp" transition followed by "flat" level between transitions is due to the finite transition time between sample (i.e. rise/fall times) along with the impedance that the DAC sees at its output that effects its response and settling time.

If you were to connect the ideal DAC output to a spectrum analyzer, you would see the desired sine wave fundamental waveform along with images at  N*FDAC +/- FOUT.  A non-ideal DAC will also produce harmonics of the sine wave (along with harmonics associated with images) as well as clock feedthrough.

To see a nice sinewave on scope, one will need to filter out all the images above the Nyquist Frequency of FDAC/2.  Due to the transition region of an analog filter, typically one specifies a filter with a cut-off frequency that is around 0.4 *FDAC.   For instance, when operating at 200 MSPS, one would use a 80 MHz low pass filter to suppress the DAC's 1st image at 120 MHz and subsequent images at 280 MHz, 320 MHz, 480 MHz, ext.

It looks like the DAC is now working fine.  When you sample at 25 MSPS, one can easily see the DAC produce closer to its ideal stair-case waveform where it transitions between different samples and holds the level until the loading the next sample.   The reason that it is not infinitely "sharp" transition followed by "flat" level between transitions is due to the finite transition time between sample (i.e. rise/fall times) along with the impedance that the DAC sees at its output that effects its response and settling time.

If you were to connect the ideal DAC output to a spectrum analyzer, you would see the desired sine wave fundamental waveform along with images at  N*FDAC +/- FOUT.  A non-ideal DAC will also produce harmonics of the sine wave (along with harmonics associated with images) as well as clock feedthrough.

To see a nice sinewave on scope, one will need to filter out all the images above the Nyquist Frequency of FDAC/2.  Due to the transition region of an analog filter, typically one specifies a filter with a cut-off frequency that is around 0.4 *FDAC.   For instance, when operating at 200 MSPS, one would use a 80 MHz low pass filter to suppress the DAC's 1st image at 120 MHz and subsequent images at 280 MHz, 320 MHz, 480 MHz, ext.