PLL Filter

Hi dgun ,

Your query is acknowledged. We'll contact the product owner to look into this and get back to you.

Regards,
Zaeefa

Thank you. As I look more into it, I also need more information to design a loop filter. The PLL flicker and noise FOM and the VCO phase noise and kv. In other words, the datasheet doesn't have enough information to design a loop filter. The adisimpll program also doesn't have ad9172 as an option.

Figure 84 shows the recommended loop filter and how it is connected to FILT_FINE, FILT_COARSE, FILT_VCM pins. You can customize the filter according to the PFD frequency, reference clock and phase noise, and DAC output phase noise requirements. The PLL coarse loop filter is set to 33nF, which does not impact phase noise.

Yes, but I would like to customize the filter and there is not enough information in the datasheet to do that. I could work backwards from the above information, but it would be a lot easier to work forwards. Information that would be required would be kv of the VCO, open-loop phase noise of the VCO and PLL flicker and noise FOMs.

Hello,

You are correct that C3 does not impact phase noise response with R1, C1 and C2 being the components that are modified when optimizing PLL response. To optimize filter settings, download ADIsimPLL using link below and select the AD9172 device as shown below which allows to modify the AD9172 settings and PLL/VCO performance.

Regards


ADIsimPLL | Analog Devices

Hello,

You are correct that C3 does not impact phase noise response with R1, C1 and C2 being the components that are modified when optimizing PLL response. To optimize filter settings, download ADIsimPLL using link below and select the AD9172 device as shown below which allows to modify the AD9172 settings and PLL/VCO performance.

Regards


ADIsimPLL | Analog Devices

Thanks. That's what I needed. Not sure how I missed that.