PLL

Hi Lily0303 ,

Thank you for your interest in AD9148. The product owner will look into this and get back to you as soon as possible.

Regards,
Zaeefa

Hi Lily0303 ,

For VCO Band settings, please follow Figure 75. Your VCO band configuration sets to 0xC or 12, that falls around 1200MHz, however your calculated VCO frequency is 1920MHz (120MHz x 4 x 4).

0x06 [bit 7], PLL lock lost, indicates that the PLL that was previously locked has unlocked from the reference signal.

Hi Deferson，

Thanks for your reply, PLL locked successfully after I changed register 0X0A to 0xF5.

I still have a question, I tried the DIERECT mode（PLL disable）, does DACCLK frequency have to be greater than 2 times the DATA rate to satisfy the sampling theorem？

Hi Lily0303 ,

Data Rate depends on the interpolation (1x, 2x, 4x, 8x) settings. AD9148 has 3 half-band filters (0x1C, 0x1D, 0x1E) [bit 0] to set your interpolation. Your calculation would be Fdatarate = Fdacclk / interpolation.

Hi Deferson，

Thank you for your patience！

Since I need to output 240M bandwidth broadband signal with 9148, I will lose 20% bandwidth after using HB1, so I don't want to use HB filters, is this correct？

Hi Lily0303 ,

Yes, you can bypass the half-band interpolation filters if you have no passband requirements. 

Hi,Deferson,

Please help me look at this configuration mode: Data rate 240M, DACCLK 240M, bypass HBs. After I configured the 9148 in this way, the output spectrum(white noise) bandwidth exceeded 240M and was close to 280M, which was very different from the 240M I wanted. What is the problem with this way of configuration?
Thank you.

Hi Lily0303 ,

1. Would you be able to provide your capture?
2. What evaluation board and data pattern generator are you using?
3. What software platform are you using?

Thank you.

Hi Deferson,

1.I am using the custom board with AD9148 and using FPGA(Xilinx K7) to generate data.

2.I use the CF_DAC_IF  interface provided by ADI to tranport frame or data (data rate is 240M)from FPGA to AD9148.

Thank you