Category: Hardware
Product Number: AD9173
We are using DAC P/N AD9173 in our design to generate 950MHz - 1550MHz. The JESD204B signal source is a Xilinx Kintex FPGA. The FPGA and DAC are on custom printed circuit boards. The DAC sampling clock is running at 4.8 GHz. The internal PLL path in the DAC is bypassed. With this configuration, we are getting poor spurious response from the DAC. The following observations while evaluating the DAC was noted down,
1. The signal in the second Nyquist zone was only 11 dBc from the fundamental.
For example if the fundamental (fo) is 1.55 GHz, my fs/2 is 2.4GHz. The image of my fundamental in the second Nyquist zone here is 3.25 GHz which is 10 dBc from my fundamental.
2. The harmonic and spurious performance is also 35 dBc.
For example if the fundamental (fo) is 1.55 GHz for fs of 4.8GHz my fs-2fo is 4.8 GHz - 3.1 GHz which is 1.7 GHz. This is only 35 dBc from my fundamental.
3. We are also getting mfo±nfi 50dBc down from our fundamental, where fo is fundamental frequency and fi is image frequency.
These are just three out of all the spurs we are getting from the DAC. Is there any way to remove the spurious levels.
