Mapping Samples for JESD204B on AD9174-FMC-EBC with Virtex Ultrascale FPGA

Hi everyone,

I am working with an AD9174-FMC-EBC board in combination with a Virtex Ultrascale FPGA. My goal is to send samples to check whether JESD204B is functioning correctly and to verify the connection setup.

However, I’m facing difficulty in sending data as mentioned in the mode table, such as mapping to M0S0 [7:0] and other related mappings.

Could anyone guide me on how to properly map my samples with the expected mapping as outlined for the AD9174? Specifically, I need assistance on how to format the data in my FPGA design to match the expected format for successful JESD204B communication.

Any help or example code snippets would be greatly appreciated.

Thank you!