ad9163

Hi wuzhoukeji ,

Thank you for your interest in AD9163. Your query is acknowledged and will be responded by the product owner (MohammedHossain ) soon.

Regards,
Zaeefa

Sysref (4.6875MHz) and device clk are generated by the same clock source.
The return values of the relevant synchronization registers are as mentioned above, but there is no detailed explanation on how to use these values and what they represent. Besides, in order to achieve synchronization, how should the registers 0x034, 0x035, 0x036, and 0x302 be used? How can I ensure that the phase relationship between the device clock and sysref remains stable and unchanged?

Mohammed_Hossein could you give some suggestions?

PDF

 For optimum deterministic latency timing skew of SYREF among multiple devices should be minimum. Subclass-1 allows the link to be synced to within four DAC clock periods. You will find more information concerning MCS procedure in the attached file.

PDF

 For optimum deterministic latency timing skew of SYREF among multiple devices should be minimum. Subclass-1 allows the link to be synced to within four DAC clock periods. You will find more information concerning MCS procedure in the attached file.

Thank you

Can AD9163 achieve a synchronization error of less than 100ps for 4 chips? （DAC CLOCK = 6GHz） 

I have tried following the steps in the information you provided, but found that the values read by registers 0x0037 and 0x038 change after each power on and off. Which set of return values should I use to set the delay value?

MohammedHossain