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ad9163

Category: Datasheet/Specs
Product Number: AD9163

The AD9163 chip has a working clock of 6GHz, a line rate of 7.5Gbit/s, and 204b parameters of F=1 and K=32.
When I am debugging the synchronization of 4 AD9163 chips, I access registers 0x037 and 0x038. The manual explains the phase relationship between the 4-fold DAC clock and the sampled SYSREF. So, how should I use this return value to achieve synchronization? Most of the return values are 0x0fe0, 0x0fc0, 0x0f80, 0x0f00. What do these values represent?

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  • Sysref (4.6875MHz) and device clk are generated by the same clock source.
    The return values of the relevant synchronization registers are as mentioned above, but there is no detailed explanation on how to use these values and what they represent. Besides, in order to achieve synchronization, how should the registers 0x034, 0x035, 0x036, and 0x302 be used? How can I ensure that the phase relationship between the device clock and sysref remains stable and unchanged?

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