AD3541R: Clarification on Asserting LDAC pin in AD3541R DAC running in Dual SPI DDR Streaming mode

Everything looks correct in the timing diagram. I have two suggestions to analyze the problem:

• Check that t10 (last falling edge of SCLK sampling data to LDAC assertion) is met (7.5 ns min)
• Try writing the DAC register (0x2A) to verify that initialization and communication are correct. Leave LDAC high.

It is also worth checking that you can clear the error status register (0x17). If the chip is working properly, only bit 0 should be asserted (write 0x01 to clear it). The ALERT pin should go high.

Just a note on using LDAC in synchronous mode. Unless both channels need to change at the same time, using LDAC does not provide any advantage in terms of timing accuracy if it is derived from the same logic as SCLK. It has a time penalty compared to writing the DAC register and a timing constraint because it must be asserted before the last bit of the next word is latched in.

Hi Antonius, thank you for your response. I am referring to AD2541R Rev A datasheet and I have the below queries for your reply.

1. As per the sheet page 8, Figure 7, the address should be serialized only on SDIO0, therefore for 7-bit addressing, it takes 8 clock cycles (includes Write bit). I could not any reference where address should be serialized on SDIO0 and SDIO1 wither in single data rate or double data rate. Please let me know if address should indeed be sent over both lines for DDR.

2. I did indeed misrepresent the edge where the last bit is being sampled. The last bit is actually being sampled at falling edge while the first bit is being sampled at rising edge. As per the image I submitted, the data is changed twice per cycle and is changing between the cycle. The FPGA clock is also 4 times the SCLK.

3. Once I am starting the stream, CS remains low unless reset. Only LDAC is being changed that too after the last bit is sent. 

Please review my reply and help clarify on how to properly send the data to DAC_INPUT_16B register with LDAC involved. Thank you very much for your time.

Hi Antonius, thank you for your response. I am referring to AD2541R Rev A datasheet and I have the below queries for your reply.

1. As per the sheet page 8, Figure 7, the address should be serialized only on SDIO0, therefore for 7-bit addressing, it takes 8 clock cycles (includes Write bit). I could not any reference where address should be serialized on SDIO0 and SDIO1 wither in single data rate or double data rate. Please let me know if address should indeed be sent over both lines for DDR.

2. I did indeed misrepresent the edge where the last bit is being sampled. The last bit is actually being sampled at falling edge while the first bit is being sampled at rising edge. As per the image I submitted, the data is changed twice per cycle and is changing between the cycle. The FPGA clock is also 4 times the SCLK.

3. Once I am starting the stream, CS remains low unless reset. Only LDAC is being changed that too after the last bit is sent. 

Please review my reply and help clarify on how to properly send the data to DAC_INPUT_16B register with LDAC involved. Thank you very much for your time.

You are right. See the corrected answer above and some suggestions for debugging.

Hi Antonius, thank you for the suggestions. 

1. t10 is satisfying the minimum time difference.

2. I tried writing to 0x2A register, with LDAC high and still there is no output on Analog output pin. May I know if LDAC should be masked in HW_LDAC_16 register.

Also, may I know the timing details on sending the instructions to the DAC in Dual SPI streaming mode write operation. I am looking for information similar to Figure 7 in page 59 of the datasheet. Any similar information would be greatly helpful.

Thank you.

Everything is correct from the protocol point of view.

You should serialize 0x2A on SDIO0 with SDR, then switch to DDR serializing data on SDIO1 and SDIO0.

There is no need to set any bit mask to get the output updated when writing the DAC register.

Timings in dual SPI mode are all included in figure 7.

You can check if the chip is understanding the commands measuring the ALERT pin. This pin must go high when you clear the error status register writing 0x17 0xFF. It should stay high if there are no protocol errors.

The voltage on the DAC output must be 0V (high impedance) at power up. If you see the output at the rails, it means that the amplifier is damaged.

Thank you Antonius. I was able to run the DAC in streaming mode with 0x2A. I unmasked the HW LDAC and left it high. Thank you once again for your help on this.