AD3541R: Clarification on Asserting LDAC pin in AD3541R DAC running in Dual SPI DDR Streaming mode

Question

Hi, I am trying to generate analog waveforms on AD3541R DAC. I am trying to run it in Streaming mode with SDIO0 and SDIO1 (Dual SPI Write mode) with double data rate. I am trying to write the DAC data to 0x34. I have kept the addressing as descending and stream mode length to 0x02 so that I am accessing 0x34 and 0x33 registers n streaming mode. I have referred the datasheet and having difficulty in understanding on when to assert LDAC pin. I am using hardware LDAC pin. The data is sent in this order: CS is asserted low, in parallel on SDIO0 line: 8 bits of instruction phase (W+0x34), then 4 MSB (0x34 even bits) and then 4 LSB (0x33 even bits); on SDIO1 line: 8 bits of 0s as address is not necessary, then 4 MSB (0x34 even bits) and then 4 LSB (0x33 even bits). Once these bits are sent, on the LDAC is asserted low, wait for the SPI posedge to sample the LDAC and then in next, LDAC is de-asserted and data bits is sent again. I am unable to generate the waveform. Could you please let me know the right way to implement using LDAC assertion. Timing diagram also attached 
 PDF

Antonius · Accepted Answer

Everything is correct from the protocol point of view. 
 You should serialize 0x2A on SDIO0 with SDR, then switch to DDR serializing data on SDIO1 and SDIO0. 
 There is no need to set any bit mask to get the output updated when writing the DAC register. 
 Timings in dual SPI mode are all included in figure 7. 
 You can check if the chip is understanding the commands measuring the ALERT pin. This pin must go high when you clear the error status register writing 0x17 0xFF. It should stay high if there are no protocol errors. 
 The voltage on the DAC output must be 0V (high impedance) at power up. If you see the output at the rails, it means that the amplifier is damaged.)

Antonius · Answer

Everything looks correct in the timing diagram. I have two suggestions to analyze the problem: 
 
 Check that t10 (last falling edge of SCLK sampling data to LDAC assertion) is met (7.5 ns min) 
 Try writing the DAC register (0x2A) to verify that initialization and communication are correct. Leave LDAC high. 
 
 It is also worth checking that you can clear the error status register (0x17). If the chip is working properly, only bit 0 should be asserted (write 0x01 to clear it). The ALERT pin should go high. 
 Just a note on using LDAC in synchronous mode. Unless both channels need to change at the same time, using LDAC does not provide any advantage in terms of timing accuracy if it is derived from the same logic as SCLK. It has a time penalty compared to writing the DAC register and a timing constraint because it must be asserted before the last bit of the next word is latched in.

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AD3541R: Clarification on Asserting LDAC pin in AD3541R DAC running in Dual SPI DDR Streaming mode