AD9162-Reference clock design

Question

Hi all, 
 I would like to ask a question about AD9162 EVB. The block diagram is below: 
 
 The output of ADF4355 is divided by 4 by using HMC362 and it goes to AD9508 fan out buffer. 
 ADF4355 has an internal divider (1,2,4,8,16,32,64) and it can be directly connected to AD9508 without HMC362. 
 What is the reason of using an external divider, HMC362, instead of using ADF4355's internal one? 
 Regards,

zpandangan · Accepted Answer

Hi mnb123 , 
 The internal RF divider is shared by the primary (RF OUT A) and auxiliary (RF OUT B) outputs of the ADF4355 and is used mainly to generate the desired frequency outside the range of its VCO. This means that RF OUT B produces the same output as RF OUT A. 
 If the eval board is configured such that the on-board PLL is used as the clock source, the ADF4355 has to provide both the DAC clock and the SYSREF signals through the AD9508 (to ensure synchronization and phase alignment). To drive this clock fanout buffer with an acceptable input from the ADF4355 without limiting the clock frequency going to the DAC, the HMC362 is there to divide-down the output from the PLL to a frequency below 1650 MHz. 
 
 Regards, Zaeefa)

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AD9162-Reference clock design