Inquiry about AD9163 Clock Settings and Clock Distribution

Hello,

Answers to your questions are as follows:

1) No issues since the maximum complex bandwidth with 12x interpolation is 400 MHz when operating with IQ rate of 500 MSPS. 

2) The interpolation filters used fixed optimized coefficients so they are not programmable.

3)  Not clear about the question.   Assumption is that the complex signal being -160 MHz to +160 MHz will be upconverted by complex NCO to some RF frequency.  For practical purposes (filtering of DAC images), this RF frequency will be no greater than 0.4 x FDAC...............hence limit is 2.4 GHz when operating in NRZ mode.  Note datasheet plot below shows case for FDAC=5 GHz with fundamental and image highlighted for FOUT=2 GHz case.

It is possible to operate to use the 2 x NRZ mode to reduce the the FDAC_CLK to 3 GSPS  (i.e. 8x interpolation at IQ rate of 500 MSPS and then enable the 2X FIR85 filter) so that the effective FDAC rate becomes 6 GSPS (where both rising and falling edge of DAC's input clock are used for updating new data).

Thank you for the good response.

I would like to clarify question 3 again. We are using a 6 GSPS clock, but we want to reduce the data rate to below 100 MHz, not 500 MHz. Even with an interpolation of x24, the lowest data rate we can achieve is 250 MSPS. Therefore, I am wondering if it is possible to lower the 6 GSPS clock value internally rather than using external PLLs or similar methods. Looking at the AD9163 Block Diagram, I noticed there is a block for distributing the clock. I am curious if this block can lower the 6 GSPS clock, so I am inquiring about this.

Hello,

The DAC clock rate can be lowered down to 1.5 GSPS according to the specification below.  If you IQ rate is reduced to 100 MSPS with interpolation by 24x than the DAC clock rate is 2.4 GSPS.  Note the AD9163 does NOT include on-chip clock multiplier hence the DAC clock must be provided by external clock source that is equal to FDAC.  Also, the clock distribution circuit shown in functional block delivers divided down clocks to the digital filters and JESD204 core.  With 24x interpolation, many options exist for the # of lanes, L, that can be used..........however working with L=1 or 2 would make the most sense to keep lane rates in the 2-4 GBPS range.