Hello AD,
I am familiar with document CN0432 and understand how to construct a high-speed IQ transmitter.
I am having an issue with the DAC AD9139 in our hardware design, where two DACs are connected to an FPGA Xilinx Ultrascale+. Due to the FPGA's clock speed limitations, we must use the built-in PLL in the AD9139. We are unable to configure both AD9139s to be synchronized, i.e., to have the same latency.
We need to utilize two features advertised in DAC AD9139 simultaneously: the PLL for acquiring DAC clock and the synchronization of multiple devices. The datasheet does not state that these two functions are mutually exclusive.
Parameters:
DAC update rate: 1600 Msps.
Interpolation: 2.
DCI frequency: 400 MHz.
Frame clock frequency: DCI/8 = 50 MHz.
REFCLK/SYNCCLK frequency 200 MHz.
I used a PLL due to the FPGA's frequency limitation. The REFCLK/SYNCCLK input is currently 200 MHz. A lower REFCLK would be 1600 / 16 = 100 MHz (limitation of AD9139).
The sequence to start the FIFO system from the AD9139 datasheet on page 31 does not always lead to the correct synchronization of both AD9139s. Occasionally, there is a latency difference.
Please outline the procedure for achieving synchronization of two AD9139s connected to an FPGA without using additional external clock generators.
Thank you.
