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Question about AD9106 DDS output modulated by waveform from SRAM

Category: Datasheet/Specs
Product Number: AD9106

Hi
I'm trying to transmit DDS sine wave modulated by SRAM. Below is my transmit setting:

Sine wave : 2MHZ, 5 cycles

f clock frequency :  160MHZ

I wrote 30 points into SRAM, the first 3 points are 2047, the last 27 points are 0.The start_address of all 4 DAC channels is 0x0.The stop_address of all 4 DAC channels is 0x1D.
The following is the result of the oscilloscope measurement,

2 points =2047, 28 points =0

5 points2047, 25 points=0

25 points=2047, 5 points=0

About 5 points will be one cycle of the sine wave, that is to say, the resolution of the DDS is about 5*2=10MHZ. In my original expectation, the number of points in SRAM should be 160/2*5=400 and the resolution equals to DAC clock frequency, but in the actual measurement, only the first 30 points affect the output of the DDS. Is the resolution originally designed to be 10MHZ? Or is there something wrong with my settings?

0001 : 0e00
0002 : 0000
0003 : 0000
0004 : 003f
0005 : 003f
0006 : 003f
0007 : 003f
0008 : 0000
0009 : 1f00
000a : 1f00
000b : 1f00
000c : 1f00
000d : 0000
000e : 4000
001d : 0000
001e : 0001
001f : 0000
0020 : 01df
0022 : 0000
0023 : 0000
0024 : 0000
0025 : 0000
0026 : 3333
0027 : 3333
0028 : 0011
0029 : 03bf
002a : 0001
002b : 0001
002c : 0003
002d : 0000
002e : 0000
002f : 0000
0030 : 0000
0031 : 0000
0032 : 0f00
0033 : 0f00
0034 : 0f00
0035 : 0f00
0036 : 0001
0037 : 0200
003e : 0333
003f : 3300
0040 : 0000
0041 : 0000
0042 : 0000
0043 : 0000
0044 : 0000
0045 : 0000
0047 : 0000
0050 : 0000
0051 : 0000
0052 : 01d0
0053 : 0005
0054 : 0000
0055 : 0000
0056 : 01d0
0057 : 0005
0058 : 0000
0059 : 0000
005a : 01d0
005b : 0005
005c : 0000
005d : 0000
005e : 01d0
005f : 0005
0060 : 0000

Register table before running

Parents
  • Hi  ,

    With a 2MHz sinewave output at 160 MHz DAC clk frequency, there should be a minimum of 80 SRAM addresses used. At default settings, the 5 points you mentioned should only generate about 1/16th of a cycle like in the capture below. 

    Looking at your register settings, the register that will have an effect on your output is the Hold field (Register 0x28 [11:8]). The Hold field specifies how long the sample (in SRAM) is held in terms of DAC CLK periods. This is usually used when generating output from SRAM. Increasing the Hold field will also increase the times the DAC value in SRAM is held. Nominally, this is set to 1. For example, if the DAC CLK is 100 MHz and Hold field is 1, each sample in SRAM is held for 1/100MHz or 10 ns. If Hold field is 10 for this example, then each sample in SRAM is held for 10*1/100MHz or 100ns. Note that changing the Hold field will also change the output frequency from SRAM (assuming a periodic output waveform like a sinewave). 

    For your case, the Hold field in 0x29 is set to 0, which means the value in SRAM will be held for 16 samples (We will revise this statement in the datasheet). This is why you are able to create 1 cycle with just 5 points. 

    Best regards,
    Marco

Reply
  • Hi  ,

    With a 2MHz sinewave output at 160 MHz DAC clk frequency, there should be a minimum of 80 SRAM addresses used. At default settings, the 5 points you mentioned should only generate about 1/16th of a cycle like in the capture below. 

    Looking at your register settings, the register that will have an effect on your output is the Hold field (Register 0x28 [11:8]). The Hold field specifies how long the sample (in SRAM) is held in terms of DAC CLK periods. This is usually used when generating output from SRAM. Increasing the Hold field will also increase the times the DAC value in SRAM is held. Nominally, this is set to 1. For example, if the DAC CLK is 100 MHz and Hold field is 1, each sample in SRAM is held for 1/100MHz or 10 ns. If Hold field is 10 for this example, then each sample in SRAM is held for 10*1/100MHz or 100ns. Note that changing the Hold field will also change the output frequency from SRAM (assuming a periodic output waveform like a sinewave). 

    For your case, the Hold field in 0x29 is set to 0, which means the value in SRAM will be held for 16 samples (We will revise this statement in the datasheet). This is why you are able to create 1 cycle with just 5 points. 

    Best regards,
    Marco

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