Category: Software
Product Number: AD9152
From the FPGA side, there are synchronization character stream in the SERDIN lines. But DAC is not pulling syncout to high?. What can be the reason for it? We gave the reference clock to DAC (Device clock) and IP core(TX) from same clock chip (AD9528). DAC refclk = 1000MHz and IP core refclock = 125MHz. DAC PLL and SERDES PLL is locking as expected. 0X03B (SYNC_STATUS) reg gives 1101 output. But sync is not achiving.
