We plan to design an ad9172 custom board with 2 SMA output ports, one for I (DAC0 output), and the other for Q (DAC1 output).
We plan to use Single-Link JESD mode 8 to transfer the FPGA I data to DAC core 0 & Q data to DAC core 1. Please advise if it's valid.
Thank you.
Bellow gives the summary:
FPGA IQ data rate=1.2G, Fdac=4.8G, ch-interpolation=1, main-datapath-interpolation=4
Use built-in PLL, Fref=300M, M=1, N=4, so Fvco=(8xNxFref)/M=9.6 G
Fdac=Fvco/2 = 4.8 G,