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Single link JESD mode 8

Category: Datasheet/Specs
Product Number: AD9172

We plan to design an ad9172 custom board with 2 SMA output ports, one for I (DAC0 output), and the other for Q (DAC1 output).

We plan to use Single-Link JESD mode 8 to transfer the FPGA I data to DAC core 0 & Q data to DAC core 1. Please advise if it's valid.

Thank you.

Bellow gives the summary:

FPGA IQ data rate=1.2G, Fdac=4.8G, ch-interpolation=1, main-datapath-interpolation=4

Use built-in PLL, Fref=300M, M=1, N=4, so Fvco=(8xNxFref)/M=9.6 G

Fdac=Fvco/2 = 4.8 G, 

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  • That is valid. You will want to use the below modulator switch configuration, correct? On the 9172 splitting the I and Q data to the separate dac cores is done before the main datapath NCO, so you would not be shifting baseband data at all in this case, since you are bypassing the channel NCO, and sending the I and Q streams to the dac cores prior to the main datapath NCO. If you wanted to use the main NCO and send the NCO I Q outputs to the dac cores instead you would need to use the AD9174/5/6 which have that option. 

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  • That is valid. You will want to use the below modulator switch configuration, correct? On the 9172 splitting the I and Q data to the separate dac cores is done before the main datapath NCO, so you would not be shifting baseband data at all in this case, since you are bypassing the channel NCO, and sending the I and Q streams to the dac cores prior to the main datapath NCO. If you wanted to use the main NCO and send the NCO I Q outputs to the dac cores instead you would need to use the AD9174/5/6 which have that option. 

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