JESD lowest possible Data rate, DAC Sampling rate and output frequency in AD9144

Hi Avinash,

Your query is acknowledged. Please give time for the product owner to look into this and provide you with a response.

Regards,
Zaeefa

Hi DataCon ,

The configuration you mentioned is possible with the AD9144. The minimum JESD204B lane rate can be found in the Digital Specs table (Page 7). The minimum lane rate is 1.44 Gbps, which is placed in the "Maximum" column because a lower lane rate can be achieved, however performance may not be guaranteed or the SERDES PLL may not lock. 

The relationship between the JESD lane rate and the DAC clock frequency is indicated below (found in Page 35 of datasheet). DAC Rate is the DAC sampling rate, and M and L are JESD204B parameters whose values are based on the mode of operation (listed in Page 49 of datasheet). 

The lowest output frequency can go to 0 as seen in the typical performance characteristics. If you will have 50MHz sampling rate, you can configure the device to bypass interpolation and operate at JESD Mode 3 or Mode 7 to have the Lane Rate at 2Gbps. 

Best regards,
Marco

Hi Macro,

Thanks for answering the questions.

I have few more questions based on your responses.

For your point, "The minimum lane rate is 1.44 Gbps, which is placed in the "Maximum" column because a lower lane rate can be achieved, however performance may not be guaranteed or the SERDES PLL may not lock"

it means at minimum rate of 1.44Gbps, the Serdes PLL may not lock and performance cannot guarantee? or our application of 50MHz sampling rate and output signal of 0 to 1MHz cannot be created as clean output?

Data rate refers to JESD input rate. Is it correct?

As per your suggestion,

For mode 3: M=4, L=2 or mode 7, M=2, L=1 per link in dual link mode, 

DAC rate=50Msps, Interpolation factor=1 (bypass mode), Data rate = 50/1 = 50Msps;

Lane rate= (20*50*4)/2= 2000Msps

So Link rate = 2 x 2000 = 4000Msps (No of lanes per link x Lane rate)

Is this correct?

I have another query in above DAC rate table. 

Max DAC sampling rate with interpolation factor 1 is 1060Msps. But what could minimum sampling rate?

Will it be 2 or 2.5 times the actual output signal rate (as per Nyquist criteria)?

Secondly what is adjusted DAC update rate? In this with higher interpolation factor, the DAC rate is reducing (example: 350Msps with x8 interpolation)?

Thanks, Avinash

Hello,

Considering the low sample rate of 50 MSPS and signal reconstruction of 0 to 1 MHz........suggest you look at the dual AD9117 that supports interleaved CMOS data input.   Although it is not available in Quad........it represents the lowest cost solution and easiest to implement vs any JESD204 interface (with these DAC's specifically designed to handle much higher data rates hence added complexity of JESD204).

www.analog.com/.../ad9114_9115_9116_9117.pdf

hi, Ok, interleaved CMOS mode, is it possible to use 6 pins only (and remaining 6 pins as No connect in Hardware) for 12 bit resolution?

hi, Ok, interleaved CMOS mode, is it possible to use 6 pins only (and remaining 6 pins as No connect in Hardware) for 12 bit resolution?