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JESD lowest possible Data rate, DAC Sampling rate and output frequency in AD9144

Category: Hardware
Product Number: AD9144

Hi,

What will be the minimum or lowest possible input JESD Data rate, lowest possible DAC sampling frequency, and lowest possible output current frequency in AD9144 DAC IC?

we want 50MHz sampling rate and output current of 0 to 1MHz signal?

Is it possible or not?

Thanks in advance, Avinash

Parents
  • Hi Avinash,

    Your query is acknowledged. Please give time for the product owner to look into this and provide you with a response.

    Regards,
    Zaeefa

  • Hi  ,

    The configuration you mentioned is possible with the AD9144. The minimum JESD204B lane rate can be found in the Digital Specs table (Page 7). The minimum lane rate is 1.44 Gbps, which is placed in the "Maximum" column because a lower lane rate can be achieved, however performance may not be guaranteed or the SERDES PLL may not lock. 

    The relationship between the JESD lane rate and the DAC clock frequency is indicated below (found in Page 35 of datasheet). DAC Rate is the DAC sampling rate, and M and L are JESD204B parameters whose values are based on the mode of operation (listed in Page 49 of datasheet). 

    The lowest output frequency can go to 0 as seen in the typical performance characteristics. If you will have 50MHz sampling rate, you can configure the device to bypass interpolation and operate at JESD Mode 3 or Mode 7 to have the Lane Rate at 2Gbps. 

    Best regards,
    Marco

Reply
  • Hi  ,

    The configuration you mentioned is possible with the AD9144. The minimum JESD204B lane rate can be found in the Digital Specs table (Page 7). The minimum lane rate is 1.44 Gbps, which is placed in the "Maximum" column because a lower lane rate can be achieved, however performance may not be guaranteed or the SERDES PLL may not lock. 

    The relationship between the JESD lane rate and the DAC clock frequency is indicated below (found in Page 35 of datasheet). DAC Rate is the DAC sampling rate, and M and L are JESD204B parameters whose values are based on the mode of operation (listed in Page 49 of datasheet). 

    The lowest output frequency can go to 0 as seen in the typical performance characteristics. If you will have 50MHz sampling rate, you can configure the device to bypass interpolation and operate at JESD Mode 3 or Mode 7 to have the Lane Rate at 2Gbps. 

    Best regards,
    Marco

Children
  • Hi Macro,

    Thanks for answering the questions.

    I have few more questions based on your responses.

    For your point, "The minimum lane rate is 1.44 Gbps, which is placed in the "Maximum" column because a lower lane rate can be achieved, however performance may not be guaranteed or the SERDES PLL may not lock"

    it means at minimum rate of 1.44Gbps, the Serdes PLL may not lock and performance cannot guarantee? or our application of 50MHz sampling rate and output signal of 0 to 1MHz cannot be created as clean output?

    Data rate refers to JESD input rate. Is it correct?

    As per your suggestion,

    For mode 3: M=4, L=2 or mode 7, M=2, L=1 per link in dual link mode, 

    DAC rate=50Msps, Interpolation factor=1 (bypass mode), Data rate = 50/1 = 50Msps;

    Lane rate= (20*50*4)/2= 2000Msps

    So Link rate = 2 x 2000 = 4000Msps (No of lanes per link x Lane rate)

    Is this correct?

    I have another query in above DAC rate table. 

    Max DAC sampling rate with interpolation factor 1 is 1060Msps. But what could minimum sampling rate?

    Will it be 2 or 2.5 times the actual output signal rate (as per Nyquist criteria)?

    Secondly what is adjusted DAC update rate? In this with higher interpolation factor, the DAC rate is reducing (example: 350Msps with x8 interpolation)?

    Thanks, Avinash

  • Hello,

    Considering the low sample rate of 50 MSPS and signal reconstruction of 0 to 1 MHz........suggest you look at the dual AD9117 that supports interleaved CMOS data input.   Although it is not available in Quad........it represents the lowest cost solution and easiest to implement vs any JESD204 interface (with these DAC's specifically designed to handle much higher data rates hence added complexity of JESD204).

    www.analog.com/.../ad9114_9115_9116_9117.pdf




  • hi, Ok, interleaved CMOS mode, is it possible to use 6 pins only (and remaining 6 pins as No connect in Hardware) for 12 bit resolution?

  • Hi  ,

    The 1.44 Gbps can be thought as the minimum "guaranteed" JESD lane rate. If you go below this range, the performance of the device is not guaranteed and the SERDES PLL might not lock. The SERDES PLL needs to lock in order to obtain an output frequency. Going below the minimum lane rate could happen in your case if you did not bypass the interpolation or operate the device at a different JESD Mode. 

    Data rate is not the same the JESD input rate. Data rate is the DAC rate (50 MHz in your case) divided by the Interpolation factor (can be 1x, 2x, 4x, or 8x). On the other hand, JESD input rate is the term "LaneRate" in the formula. 

    Regarding your 3rd question, I haven't encountered the term 'Link Rate' before, but if you mean that the Link rate is the sum of all the lane rates for a specific link, then the formula you provided is correct. Essentially, dual link mode sets up 2 independent JESD204B links (Link 0 and Link 1) allowing each link to be set independently. Note that Link 0 and Link 1 must have identical parameters. 

    The adjusted DAC update rate is just the Maximum DAC update rate divided by the Interpolation factor. Adjusting the 2800 MSPS maximum update rate in account of the 8x interpolation gives 350 MSPS update rate. 

    The minimum sampling rate is not indicated in the datasheet. However, you can use the formula provided in Page 49 of the datasheet and use the JESD Lane Rate as the limiting factor. Based on the formula, the minimum guaranteed lane rate is 1.44 Gbps. This makes the minimum sampling rate (assuming Mode 0 operation) at 36 MHz. JESD interface is mostly used for higher sampling rates and higher frequency outputs. As mentioned by PMH2023 in a reply, using JESD interface for your application would be too much for a 0-1 MHz output. It's best to use a DAC with a lower speed grade. 

    Best regards,
    Marco

  • hi JMMina,

    Thanks for clarifying all points and suggestions.