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AD9102 SRAM Writing data rate calculation

Category: Datasheet/Specs
Product Number: AD9102

Hello,

     The product data sheet shows the SRAM SPI write timing calculation formula (2 + 2 × 4096) × 8/(2 × fSLCK), As per this we can fit the pattern waveform which is having 180 MSPS pattern.

     Can anyone please help on whats the time taken to write entire SRAM to SPI and read the entire SRAM. Please help me with the actual calculations.

    Also can you please explain the calculation too. I am in need of urgent reply

Regards,

Manu

Top Replies

  • Hi  ,

    Thank you for your interest in AD9102.  will look into this and get back to you as soon as possible. 

    Best Regards,
    Marco

  • Hi Manu,

    The Double SPI Write mode is available only for the AD9106 and not for the AD9102 (see AD9102 FAQ8). However, the time it takes to write the entire SRAM (tWSRAM) for the other SPI modes (3-wire and 4-wire) can be derived from the same expression, which would be [2 + (2 * 4096)] * 8/fSCLK (note the exclusion of 2 as a multiplying factor for fSCLK).

    Proof:

    No. of command bits: 16
    No. of data bits: 16
    No. of SRAM registers: 4096

    tWSRAM = tCOMMAND CYCLE + (4096 * tDATA TRANSFER CYCLE)
                  = (16 * 1/fSCLK) + [4096 * (16 * 1/fSCLK)]
                  = [16 + (16 * 4096)]/fSCLK
                  = [2 + (2 * 4096)] * 8/fSCLK

    where: fSCLK = SPI clock rate (up to 80 MHz based on Tables 3 and 4 of the datasheet)

    The above formula is true when the auto-decrement feature is used (i.e., the CSB bit stays low beyond the first data word and the SPI port automatically decrements the register address, allowing multiple writes to contiguous addresses) beginning at the 0x6FFF address space.

    The time it takes to read the entire SRAM (tRSRAM), on the other hand, would be more than twice as long since there is no auto-decrement feature for this operation. This means that the command cycle has to be repeated for all SRAM registers. Assuming that the SRAM registers are accessed consecutively with the CS bit set back to high right after the data transfer for exactly one SCLK cycle before it goes low again for the next read command, this value can be estimated through the following simplified equation:

    tRSRAM = 4096 * (tCOMMAND CYCLE + tDATA TRANSFER CYCLE + 1/fSCLK)
                 = 4096 * [(16 * 1/fSCLK) + (16 * 1/fSCLK) + 1/fSCLK]
                 = 4096 * 33/fSCLK

    Please note that the auto-decrement feature and how it is applicable only for the write operation in SRAM are contrary to what is specified in the datasheet. Rest assured that document revisions are currently being worked on to include these corrections.

    Hope this helps.

    Regards,
    Zaeefa