Hi,
in our current project we are using a LTC2000 in dual channel mode with a sampling frequency of 1.6GHz and data provided with a 400 Mhz clock driven by an FPGA.
After power-up and initialization we have no issue and we are able to generate the expected output.
In a second step we change the phase of the input digital clock and input digital data which we generate from the FPGA, and we start observing glitches on the analog output. This leads to the assumption that something is wrong during the sampling of the input data.
We also tried several times to reinitialize with the application steps described inside page 35 of www.analog.com/.../2000afb.pdf (with the exception of the point 1. which is not really feasible.) :
"""
1. Apply valid supply voltages to AVDD33 , DV DD33 ,AVDD18, DVDD18 and SVDD.
2. Write 0x01 to address 0x01 to perform a software reset.
3. Apply a clock to CKP/N at the desired f DAC frequency. The LTC2000A will generate a clock at DCKOP/N at fDAC/4.
4. Apply a clock to DCKIP/N at fDAC/4 for dual-port mode or f DAC/2 for single-port mode.
5. Apply zeroes to ports A and B (DAP/N, DBP/N) for dual-port mode, or only to port B for single-port mode.
6. Write to address 0x03 to enable the DCKIP/N LVDS receiver. Set address 0x03 to 0x01 if the LVDS clock (DCKI) and data (DA, DB) are in phase with each other. Set address 0x03 to 0x05 if they are in quadrature.
7. Write 0x03 to address 0x04 for dual-port mode, or write 0x06 to address 0x04 for single-port mode to enable the DAP/N and DBP/N LVDS receivers.
8. Wait at least 1ms for the synchronizer to finish initializing.
9. Write 0x0B to address 0x04 for dual-port mode, or write 0x0E to address 0x04 for single-port mode to set DATA_EN = 1.
"""
Do you have any hint? Were issues like ours already reported? Any other recommendations would be really appreciated,
Best Regards,
Cristian
