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AD9172 - Enable error counting

Category: Hardware
Product Number: AD9172

AD9172 discusses Error Counting for NIT, UEK, and Disparity errors. I am trying to enable error counters but am unable to do so. The system relies on SW polling rather than receiver IRQ detection, so I am also trying to enable the error count threshold hold feature. 

The sequence I am following is:

  1. Hold JESD QBD in soft reset
  2. Assert or Deassert all SYNC mask bits *
  3. Lower error threshold value from 0xFF *
  4. Enable Terminal Count Error Hold (0x488 - 0x48F)
  5. Choose and Enable the errors to monitor (0x480 - 0x487), enabling all and asserting reset
  6. Releasing reset while still maintaining enable bits (0x480 - 0x487)
  7. Release QBD soft reset

After 6, the link is setup, poor DAC signal is observed. Occasionally, the link synchronization registers (0x470 thru 0x473) will show errors. Other times, all synchronization bits will appear to be achieved. In both of these cases, with poor DAC signal, we see no errors in the error counter registers (0x490 thru 0x497)

If you see in steps 2 and 3, I have an asterisk - I have attempted to change the behavior of the error counting by adding these steps but they have no effect. 

Q: How can I properly enable error counting? It looks as though others have been able to get this to work (see  AD9172 JESD link stability issue ) 

1) Is order of operations in the "Checking Error Count" section, page 48 absolutely critical. I see that I am enabling the terminal count hold indicator before releasing the counters from reset.

2) Do IRQs need to be enabled to enable the error counting properly?

3) Is there some example sequence that should be followed, beyond what is listed in the datasheet? The drivers on github do not utilize any error counter monitoring 

Background:  I have a system with a link stability issue. I am able to get somewhat appropriate data from the DAC but there is noise. Tuning the link (emphasis and equalization, etc) can eventually provide a clean DAC output signal, which is why I am calling this a link stability issue caused by unit variation. The issues are not due to configuration or general setup sequence issues.

  • Hi  ,

    Thank you for interest in AD9172. The product owner  will look into this and get back to you as soon as possible.



  • Hi   , just wanted to give you some more information, and I have a follow up question.

    We are using PRBS tests and looking at the PRBS error counters during our lane tuning. We have seen that PRBS7 produces little to no errors, whereas PRBS31 produces many errors. Is there a recommended PRBS sequence to test or should we run through all PRBS patterns during tuning? 

  • Hi,

    You can use PRBS7 pattern and follow PHY PRBS Testing process described in the datasheet page 46.

    What are DAC and Lane rates you are using?

    What is your hardware and software setup? Do you use AD9172-FMC-EBZ + ADS7/ADS8 hardware and ACE+DPGdownloader software?


  • Hi  ,

    We are operating at both 7.5Gbps and 15Gbps lane rates, at 9GSPS. We see PRBS31 errors at the higher lane rate. We are following page 46 and using PRBS31 primarily.

    We are using custom hardware and software, with software following the guidelines and sequences in the datasheet.

    We are able to at least use the PRBS error registers but still have not been able to get the other error counters working. Any recommendations on that (see my 3 q's in the first post).

    Thank you for your help.

  • Hi,

    For your questions in the first post, yes we recommend to enable and check the error count following the steps given in datasheet in the datasheet. it is not required to enable IRQ control to use the error counts. 

    As you see errors in link establishment registers but no error in the error counter registers, this might be due to the high error count that reaches programmed threshold very fast.  When the error counter on any lane reaches the programmed threshold, SYNCOUTx± falls, issuing a sync request and all error counts are reset when a link reinitialization occurs.

    You might need to write 0 to SYNC_ASSERT_MASK (Register 0x47D, Bits[2:0]) according to Table 33 so auto link reinitialization is disabled and so error counts are not reset. 


  • Hi  ,

    I have written 0 to the SYNC_ASSERT_MASK to disable the link reinitialization but this also does not have an effect on the error counter registers. 

    During tuning, the PRBS test modes have been useful as the PRBS error counters work. Should we expected to see error counter registers for NIT, UEK, and Disparity errors function normally during PRBS test modes as well?

  • Hi,

    is LINK_PAGE (Register 0x300, Bit 2) set to 1 when setting the SYNC_ASSERT_MASK bits?