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Category: Hardware
Product Number: ad9739

As shown in the figure below, if the DAC sampling clock amplitude is less than the 1.2V shown in the specifications, the actual clock input amplitude Vpp is about 0.8V. Will it affect the functions of the AD9739, such as the locking of the internal DLL loop? Or will it only affect the output performance? Thank you!

  • Hello,

    While it is highly likely that the device will function properly with Vpp of 0.8 V,  the datasheet specifications are only guaranteed when operating with clock amplitudes within min/max limit.   The clock input receiver still has sufficient gain to "square-up" the input signal and present to the subsequent stages in the internal clock path hence reason why it will still function properly.   Additive jitter will depend on the "slew rate" of the input signal hence datasheet recommends use of ADCLK914 device.

    If you are in a position to experiment on your board, it could be interesting (if even possible) to reduce clock input drive to level where it the AD9739 no longer works (i.e. corrupt output spectrum, ext).   This would give you some idea on how much margin exists between your existing 0.8 Vpp and the point of failure.  One could also measure the spectral performance in terms of SFDR or ACLR to determine how performance degrades as function of clock drive level.  Ideally, one would be able to drive the clock input via a RF balun and RF signal generator to control the Vpp drive level.