PCB layout clarification

Small correction "Left side is no VIA (Top layer) , Right side has VIA (Bottom layer)

Hi Raghavan,

Thank you for your interest in LTC2000. A response to your query will be provided soon.

Regards,
Zaeefa

Hello,

It is very likely that one will be able to achieve same level of AC performance with 6-layer by following similar RF rules on as 8 layer board for RF traces.   The key is the matched delay between both data ports and the individual traces associated with each port.  The differential impedance of the through-hole vias should maintain as close to 100 ohms as possible to minimize on reflections due to any impedance discontinuity.  Suggest performing EMI simulation using some signal integrity software on the via portion to optimize the via structure. 

Hi Zaeefa,

Thanks for the clarification on the number of layers. Understand that what matters is the AC performance of the signal in the PCB. will take care of RF requirements in this 6-layer PCB similar to 8Layer.

Also matched delay between inter(Between Pair) and intra(within-pair) are taken care of by trace length matching. But inter pair of one has an additional pair of VIA(1mm VIA) as it is routed in another/different layer. whether this 1mm additional VIA on signal have any inter-pair delay concerns? if yes should I consider this VIA length as part of the length matching?

Understood the 100 ohms impedance requirement. Will follow this requirement too for VIA to minimize the reflection by providing the required Anti PAD/VIA to copper spacing in the Z axis of VIA to meet 100 ohms.

Regards,

N.Raghavan

Hi Raghavan,

I agree with PMH2023 's answer to your initial query. The PCB Layout Considerations section of the datasheet provides a discussion supporting it.

As for your second concern, the additional via length albeit small will cause delay, so I suggest factoring this in as well in the length-matching process for increased precision.

Regards,
Zaeefa