About the DAC Clock Input

Hi dqgang ,

Thank you for your interest in AD9739. Please give us time to look into this and provide you with a response.

Regards,
Zaeefa

Dear Zaeefa

        About this question，do you have some suggestion for it ？

Hi dqgang ,

Apologies for not getting back to you sooner.

The output signal from the ADCLK914 becomes acceptable for the AD9739 clock inputs when the losses due to PCB traces and impedance mismatches are accounted for. The high voltage swing from the clock buffer is typically desired as it helps ensure that the DAC's minimum required differential swing of 1.2 V_pp is satisfied.

Regards,
Zaeefa

Hi dqgang ,

Apologies for not getting back to you sooner.

The output signal from the ADCLK914 becomes acceptable for the AD9739 clock inputs when the losses due to PCB traces and impedance mismatches are accounted for. The high voltage swing from the clock buffer is typically desired as it helps ensure that the DAC's minimum required differential swing of 1.2 V_pp is satisfied.

Regards,
Zaeefa

Dear Zaeefa：

         Thank you for your kind replay~

         By the way ，about the DAC's minimum required differential swing of 1.2 Vpp，so，the single-ended swing is 0.6Vpp， am i right？（means that the differential swing is the twice of single-ended swing）

 thanks again for your kind help~

Best Regards！

     Gang

Hi dqgang ,

That is correct. Note however that the recommended minimum differential peak-to-peak voltage of the AD9739 clock receiver is ~1.4 V_pp. Kindly refer to the Clock Input Considerations section of the datasheet for further details.

Regards,
Zaeefa