AD9163 NCO Reset

Question

Hi, 
 I need to reset the NCO of the AD9163. So when the SYSREF is set, the NCO must always start at the phase. The phase value or deterministic delay do not matter, sine the phase is measured and compensated at the beginning of the measurement. 
 System: 
 DAC CLK = 6GHz Number of Lanes = 4 Subclass 1 (One-Shot Sync Mode) Unknown DAC CLK to SYSREF phase relationship. 
 After powering up, the DAC is synced by SYSREF. In the measurement mode NCO value is written over SPI and reset by SYSREF. That works so far but in some cases the reset of the NCO is not reliable (the phase jumps from SYSREF to SYSREF). I found a correlation between stability and SYSREF_PHASE0 information. When SYSREF_PHASE0 has the value 0xE0 or 0xC0 then the reset is reliable otherwise not. It looks like a timing issues between SYSREF and DAC_CLK / 4. 
 Can this problem be caused by a timing problem between SYSREF and DAC_CLK / 4? 
 Do you have a recommendation on how to solve this problem? 
 Best Regards

sml · Accepted Answer

I was able to solve the problem. It looks like there are 3 different clocks involved in the SYSREF subclass 1 synchronization / NCO reset. One is the DAC CLK the second is the DAC CLK / 4 and a lower frequency third. Considering the time window of the third one allows a stable NCO reset after synchronization. 
 I have implemented a PLL in the FPGA that can change the delay (phase) of the output clock. I perform the DAC synchronization with a delay of 0ns and then change the delay to -1.4ns. This gives me a time window of +-0.6ns for the NCO reset. The time was determined empirically.)

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AD9163 NCO Reset