AD9163 NCO Reset

Hi,

In the AD9163 datasheet on page 38, following is written:

"The SYSREF± signal is sampled by a divide by 4 version of the DAC clock. After SYSREF± is sampled, the phase of the DAC clock/4 used to sample SYSREF± is stored in Register 0x037, Bits[7:0] and Register 0x038, Bits[3:0] as a thermometer code."

1) That means in my case the SYSREF is sampled in a time window of 0.67ns is that correct?

2) How can I ensure that my SYSREF fulfills the setup and hold timing in relation to this divide-by-4 cycle?

3) Can I assume that a SYSREF_PHASE0 value of 0xE0 or 0xC0 is in the middle of the time window?

Thank you for your support

I was able to solve the problem. It looks like there are 3 different clocks involved in the SYSREF subclass 1 synchronization / NCO reset. One is the DAC CLK the second is the DAC CLK / 4 and a lower frequency third. Considering the time window of the third one allows a stable NCO reset after synchronization.

I have implemented a PLL in the FPGA that can change the delay (phase) of the output clock. I perform the DAC synchronization with a delay of 0ns and then change the delay to -1.4ns. This gives me a time window of +-0.6ns for the NCO reset. The time was determined empirically.

I was able to solve the problem. It looks like there are 3 different clocks involved in the SYSREF subclass 1 synchronization / NCO reset. One is the DAC CLK the second is the DAC CLK / 4 and a lower frequency third. Considering the time window of the third one allows a stable NCO reset after synchronization.

I have implemented a PLL in the FPGA that can change the delay (phase) of the output clock. I perform the DAC synchronization with a delay of 0ns and then change the delay to -1.4ns. This gives me a time window of +-0.6ns for the NCO reset. The time was determined empirically.