hello team,
I want to generate square waveform from 10khz to 10mhz continuously using dac ad9106 SRAM with stm32h745.. now got output for 50khz to 20Mhz but also want to minimum frequency upto 1khz, 5khz and 10khz. suggest any register value changes or any SPI frequency changes... how can i achieve minimum frequency.
Hi Dipakpatil ,
The vectors can be generated in any way, ACE Vector Generator or DPG Lite are just example softwares that ADI has to generate the vectors. If you are using ACE Vector Generator Tool, the capture below is what the UI would look like and you can play around with the values to generate the desired waveform.
Below is the square waveform with 1MHz DAC frequency and 1kHz output frequency. The resolution is changed to 12 (for 12-bit DAC), and record length is set to 3000 for a 3-cycle square waveform. Unsigned Data is unchecked for two's complement data format.
To generate a continuous waveform without delays between each pulse, the pattern period set in Register 0x29 must be equal to the length of the waveform in the SRAM.
Regards,
Marco
hello JMMina ,
I want to generate different types of waveoform like staircase, trapezoidal, arbitrary waveforms. so i put samples in range -2047 to 2048 for amplitude. i acheive this but i want to again more duration of waveform like 1ms, 2ms etc. means slow frequency waveform..
above waveform genarated using store samples in DAC AD9106 SRAM. so how can i achieve more waveform duration?
with whole stored 4095 samples in sram acquire 420uS period for single waveform.
Is it possible to generate long time/ Slow frequency waveform using AD9106 Sram?
Hi JMMina
I put value in Time control register 0x28=0x0000, and Pattern period register 0x29=0x1FFF, so using that i acquire window upto 50ns to 430us.
So what value i need to put for access full window.
In ACE software what is meaning of this
if i put this value greater than 420uS then it showing error 
Hi Dipakpatil ,
The formula for the pattern period of a waveform is below. This information is already added to the list being added to the datasheet and the datasheet is currently being revised.
The register you are changing is the Pattern period register (0x29) which is only one part of the actual pattern period. You can increase the value of that register in ACE Memory Map to its maximum (0xFFFF). You did the correct thing with setting PAT_TIMEBASE (Register 0x28) to 0x0000 - this sets the value of PAT_PERIOD_BASE to 16 DAC clock periods per PATTERN_PERIOD LSB.
If you have say 10 MHz of DAC clock frequency and have set PAT_PERIOD and PAT_PERIOD_BASE to their maximum, you will get a pattern period of 104.86 ms for the waveform (from the formula above). If you require a longer pattern period, the only thing to do is to decrease the DAC clock frequency.
Best regards,
Marco
hello JMMina
I'm trying with changing value in PAT_TIMEBASE(0x28=0xffff) Reg and PAT_PERIOD(0x29=0xffff)reg that time period in increase upto 6.5ms but waveform using 4095 samples in sram got same only upto 420uS 
and if PAT_TIMEBASE(0x28=0x0000) Reg and PAT_PERIOD(0x29=0x1fff)reg that time period upto 870us but waveform using 4095 samples in sram got same only upto 420uS
and if PAT_TIMEBASE(0x28=0x0000) Reg and PAT_PERIOD(0x29=0x0fff)reg that time period upto 112ms but waveform using 4095 samples in sram got same only upto 420uS
can you please suggest exact value to store both register? or any calculation of both. I used DAC external oscillator of 150mhz.
I want to increase window of pulse
i select below register with values. and sample store in SRAM(-2047 to 2048 and store with 2s compli)
uint16_t reg_addr[]= {0x0000,0x0001,0x0002,0x0003,0x0004,0x0005,0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x001F,0x0020,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x001E,0x001D};
uint16_t sramsquare_regval[]={0x0000,0x0e00,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x1f00,0x1f00,0x1f00,0x1f00,0x0000,0x4000,0x0000,0x000e,0x0000,0x0000,0x0000,0x0000,0x3030,0x3030,0x0000,0x1fff,0x0101,0x0101,0x0003,0x0000,0x8003,vset_hex,0x8003,0x8003,0x4000,0x4000,0x4000,0x4000,0x0001,0x0200,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x07d0,0x0000,0xFFF0,0x0000,0x0FFF,0x0000,0xFFF0,0x0000,0x0bb8,0x0000,0xFFF0,0x0000,0x0fa0,0x0000,0xFFF0,0x0000,0x0000,0x0001,0x0001};
Hi Dipakpatil ,
Please see the sample capture below. I used the AD9106 Evaluation Board to generate a 2kHz output square wave with a 1 MHz DAC CLK, with the output datapath connected to the on-board amplifier. The register settings I configured are also listed below; everything else is left at default.
* WAV2_1CONFIG (Register 0x27) = 0x0000 // DAC1 waveform read from SRAM
* PAT_TIMEBASE (Register 0x28) = 0x0001 // PAT_PERIOD_BASE and HOLD are both at maximum when set to 0
* PAT_PERIOD (Register 0x29) = 0x03E8 // gives 16 ms of Pattern period
* DAC1_DGAIN (Register 0x35) = 0x4000 // DAC gain of x1
* START_ADDR1 (Register 0x5D) = 0x0000 // Start Address at 0
* STOP_ADDR1 (Register 0x5E) = 0x1F40 // Stop Address at 500 (i.e. total of 500 SRAM addresses used)
The min. number of SRAM addresses required to generate the output frequency is given below. This is also explained in this link: (+) Question about AD9106 DDS output modulated by waveform from SRAM - Q&A - High-Speed DACs - EngineerZone (analog.com)
When generating the 2kHz square wave from SRAM, the resulting pulse width will be 0.5ms. Then, increasing the value of Hold bitfield (Register 0x28, Bits [11:8]) will increase the pulse width. Setting the Hold bitfield to 0 means holding each sample for 16 DAC CLK periods, thus the 8ms. I wanted to set the pattern period of the waveform to 16 ms to make the waveform look periodic in the output. The value set in Register 0x29 was calculated based on this actual pattern period (16us); the formula is listed my previous reply above.
Note that you can get an even longer pulse width if you generate a lower frequency (~Hz range). However, do note of the SRAM size limitation (~up to 4096 addresses only), so you also have to take note of what DAC CLK frequency you will be using. A lower output frequency will require a lower DAC CLK.
Best regards,
Marco
Hi Dipakpatil ,
There is no clock division feature (i.e. interpolation) in AD9106. You will need to divide the 156MHz clock externally so that you have a lower clock input going to AD9106. You can use the AD9514 Clock divider/distributor to divide the clock (refer to FAQ#1 in AD910x FAQs for more details).
I generated a sample below: 50kHz sine wave thru SRAM using DAC CLK of 156.25 MHz. Although this is doable, the number of SRAM addresses required to generate it is 3125 (calculated from the formula with min. number of points). Since you require a lower frequency, the number of SRAM addresses will get higher if you retain the DAC CLK constant, but SRAM size is limited to 4096. Thus, you need to lower down the DAC CLK.
Best regards,
Marco
Hi JMMina ,
Thanks for your guidance. I have try as you suggest and with ACE tools. but with 156mhz dac clock, and complete 0-4095 samples controlling only upto 420uS range.. and with changing pattern period and time base control pulse off time in ms. and amplitude control with sample (-2047 for 0v) and (2047 to full scale).
So for lower frequency or high pulse width with sram need to lower dac clock frequency. right?
Again i need one suggestion dac ad9106 differential output OUTx_P and OUTx_N. So output is 180degree of P and N like below,
blue=dac1_out1_p, red= dac1_out1_n. below waveform for full scale (-2047 to 2047)
means OUTx_P range between (0 to 500mA), and OUTx_N range between (1000mA to 500mA)? If you have some data on dac output can you please give?
and this we need one differential amplifier to single ended (0 to 1000) with additional gain set as we required.
I want to single ended output in range of 0 to 3000mV.
