Relationship between digital data errors and output signals

Hi jhshin ,

Thank you for your interest in AD9746. This is to acknowledge your query. We'll look into this and get back to you as soon as possible.

Regards,

Marco

Hi JMMina,

Are there any updates ?

Thanks,

JH

Hi jhshin ,

Thank you for your patience. Invalid timing at the inputs between clock and input data means loss of synchronization and is typically indicated by an increase in the DAC output noise floor. 

There are many sources of noise in a converter. One such source is the quantization noise which is the difference between the continuous analog signal and the quantized discrete signal. If there are timing issues between the clock and input data, the data received by the DAC will not be reliable (data could be sampled twice, missing data, sampling at data transitions, etc.) which will lead to greater quantization noise and in turn greater spurious content in the frequency domain. 

The relationship between the quantization error and the SNR is explained in these tutorials: MT-001 and MT-029. The computations are for an ideal converter, but you could imagine that if there are timing issues, the error would increase resulting to an increased RMS quantization noise level and decreased SNR value.

Let me know if you have any questions.  

Best Regards,
Marco