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AD9106 is not working but I can't figure it out why

Category: Hardware
Product Number: AD9106

I'm trying to configure the AD9106 to generate a sawtooth wave for driving the galvometer
I use an Xillinx FPGA to generate the corresponding SPI signals to communicate with the AD9106
However, whatever I changes the settings, the output of the AD9106 remains a 0.01V DC constant.

I tried to change the BGDR code of the 0x03 register, the IOREF voltage is changing correspondingly as I expected, which implies that the SPI communication is working,

I powered the AD9106 with  2.5V, the LDO pads is 1.8V, which is as I expected, indicating that the chip is not broken( I guess).

I suspect that I've done somthing wrong in the output stage circuit

The image below is our output stage circuit and AD9106 circuit schematic.

The clocking is clocked by a on board LVDS oscillator, directly fed in the CLK_P CLK_N port (which I couldn't measure it on the oscilloscope)

I need assistance Disappointed

I appreciate your help very much.

 

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  • Hi  ,

    Have you tried comparing your schematic to this page? AD9106-ARDZ-EBZ Rev B. There's a provision for Balun output (load resistor is 250ohm to GND) or Amplifier output (requires an external supply). The output path in your schematic looks like there should be separate sections for the 249Ω resistors to GND (for Balun output) and the 499Ω up to the AD8130 (for amplifier output). 

    Because you are using an LVDS oscillator as reference clock, there is also a provision in Figure 38 in Page 24 of the datasheet (Rev B) for LVDS clock drivers, there is a 100Ω termination resistor and two 0.1uF coupling capacitors are used.

    Regards,

    Marco

  • There's a provision for Balun output (load resistor is 250ohm to GND) or Amplifier output (requires an external supply). The output path in your schematic looks like there should be separate sections for the 249Ω resistors to GND (for Balun output) and the 499Ω up to the AD8130 (for amplifier output). 

    Thanks for your kind reply. I still have some questions.

    I've looked up the Evaluation board's schematic diagram, looks like the main difference is that our schmatic have a RC filter to GND on Iout-, whereas the evaluation board connects to the FB port of the amplifier. Could this be the main reason for not functioning?

    Secondly, what is the purpose of the 1K resistors that connects to P5V2 and N5V2 ?

    The supplyer of the PCB board has replaced all the active components with a new one, while the output still not as I expected. 

    Is it possible that the output net from the AD9106 (the 249 ohm to GND net) got drawn to 0V because of the connections after it ?

    Thanks you for your assistance!

  • Hi  ,

    There should be an RC filter from IOUT+ and IOUT- going to the amplifier, but the difference I see is that the feedback pin (FB) in your schematic is shorted to OUT. This could be a problem because since your Op-amp supply is ±12V (output will swing along this range), the output pins will effectively be (299Ω/499Ω)(±12V) ≈ ±4V, which is well above the Abs Max rating for the IOUT pins. Based on your schematic, DVDD is 2.5V. Can you check the voltage readings at the output pins (DAC_OUT1 P/N)?

    Although, I simulated your circuit in LTSpice and got the waveform below, is this your expected output? I used 5.2V for the supply of the amplifier similar to the evaluation board. 

    The resistors connected to P5V2 and N5V2 can be used for configurating the common mode level going to the amplifier. Nominally, the common-mode is 0V based on the resistors (R61, R63) and P5V2 and N5V2, but modifying the resistances provides a different common-mode level. Care must be taken to ensure the DAC output must still be within compliance. 

    Regards,

    Marco

Reply
  • Hi  ,

    There should be an RC filter from IOUT+ and IOUT- going to the amplifier, but the difference I see is that the feedback pin (FB) in your schematic is shorted to OUT. This could be a problem because since your Op-amp supply is ±12V (output will swing along this range), the output pins will effectively be (299Ω/499Ω)(±12V) ≈ ±4V, which is well above the Abs Max rating for the IOUT pins. Based on your schematic, DVDD is 2.5V. Can you check the voltage readings at the output pins (DAC_OUT1 P/N)?

    Although, I simulated your circuit in LTSpice and got the waveform below, is this your expected output? I used 5.2V for the supply of the amplifier similar to the evaluation board. 

    The resistors connected to P5V2 and N5V2 can be used for configurating the common mode level going to the amplifier. Nominally, the common-mode is 0V based on the resistors (R61, R63) and P5V2 and N5V2, but modifying the resistances provides a different common-mode level. Care must be taken to ensure the DAC output must still be within compliance. 

    Regards,

    Marco

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