Reference AD9786.pdf datasheet Rev. B, 2005
The data sheet does not include numbers for the setup and hold values for the SPI data lines and chip select. Only the maximum serial clock frequency is given (20MHz). Setup and hold times are shown as variables on the timing diagram but no values are provided.
Thanks, Gdms for the question. and very sorry for the delay due to the shutdown.
according to the datasheet on Page 20, CSB must be low during the entire communication cycle.
Since the communication cycle will vary based on how you configured the instruction byte on page 20 ( Like N1 and N0 in Table10 will config the number of bytes to be read or written during every cycle )
Using Fig 39 and 40 the data holding time is based on your SCLK speed (with a period of Tsclk)
Tds = the time from CSB falling edge to the next rising clock edge where the Instruction bit 7 will be sampled until the falling edge of the clock ==> Data holding time should be more than Tsclk/2 but less than the next rising clock edge
In other words, make sure to sample the Data lines on every rising edge
I hope that was helpful. please let me know if you still have questions.
Adam
The AD9786 uses the same DAC and SPI core at the AD978x products in which the SPI timing is provided in the datasheet.
