AD9106
Production
The AD9106 TxDAC® and waveform generator is a high performance, quad digital-to-analog converter (DAC) integrating on-chip pattern memory for complex waveform...
Datasheet
AD9106 on Analog.com
AD9102
Production
The AD9102 TxDAC and waveform generator is a high performance digital-to-analog converter (DAC) integrating on-chip pattern memory for complex waveform...
Datasheet
AD9102 on Analog.com
I am reaching out to seek assistance regarding some challenges I am facing with the write and read operations on the SRAM of the AD9106 devices and for generating waveform using sram. I have thoroughly studied the respective datasheets (AD9106 datasheet, pages 22-23) and also Evaluating the AD9106/AD9102 Digital-to-Analog and Waveform Generator Converter using MBED [Analog Devices Wiki] but have encountered difficulties in achieving the desired functionality.
Specifically, I am experiencing issues with:
2) Reading data to the SRAM: For writing data to the SRAM select PAT_STATUS REGISTER 1E=0X0C Read Mode. I read data that from SRAM address 0xE000-0xEFFF That calculate by 8000+starting sram address... as per code example of AD910x - Library files for EVAL-AD910x | Mbed .
but i reading value not same as write value. i attach write value output
and read value output
and haven't got expected ramp waveform
I have thoroughly reviewed the datasheets, but it appears that I may be missing some crucial steps or misinterpreting certain instructions. I would greatly appreciate it if you could provide me with guidance and clarification on the correct procedure for performing write and read operations on the SRAM of the AD9106 devices.
If possible, could you please provide me with detailed step-by-step instructions, highlighting any potential pitfalls or commonly overlooked aspects of the process? Additionally, if there are any specific register settings or considerations I should be aware of, kindly provide those details as well.
I understand that your team has extensive expertise in working with these devices, and I am confident that your guidance will help me overcome the challenges I am currently facing.
Hi Dipakpatil ,
Please refer to FAQ 4 in this link: AD9106 / AD9102 Low-Power DAC and Waveform Generator: FAQs
Please see pseudocode below and compare it to your code:
1. Set initial values of IOs.
○ RESET - logic high
○ TRIGGER - logic high
○ CS - logic high
2. Set SPI frequency and mode.
○ Clock is logic low when idle or leads with a rising edge and trails with a falling edge.
○ Data logic level should be valid during the clock rising edge and before the clock falling edge.
3. Pulse RESET to logic low then high to reset register values.
4. Proceed with register read or write. (AD9102: page 18, AD9106: pages 22-23 of datasheet)
a. If loading a pattern from SRAM, write data on SRAM registers first. (AD9102: page 23, AD9106: page 27 of datasheet)
i. To write data: Enable MEM_ACCESS bit in 0x1E register. Write left-justified data to SRAM registers, 0x6000 to 0x6FFF. Disable MEM_ACCESS bit.
ii. To read data: Enable BUF_READ and MEM_ACCESS bits in 0x1E register. After reading data from SRAM registers, disable BUF_READ and MEM_ACCESS bits.
b. Write on SPI registers. Update last bits of registers 0x1E (RUN bit) and 0x1D (RAMUPDATE bit) at the end of the write sequence.
Regards,
Marco
hello JMMina,
thanks for reply... but i trying with this also take follow of Evaluating the AD9106/AD9102 Digital-to-Analog and Waveform Generator Converter using MBED [Analog Devices Wiki].. but till facing issue... please any other suggestion? now I try to refer with AD9102 SRAM Read/Write - Q&A - High-Speed DACs - EngineerZone (analog.com)..