AD9735 DAC stops working after some time

Hi MM,

Your query is acknowledged and will be responded by the product owner soon.

Best regards,
Peevee

Another week has passed. I still haven't even received a suggestion to solve the problem. Does anyone on this forum deal with support? I understand that after paying for the ordered parts you have to cope on your own?

If this is how it is supposed to look like then unfortunately but in the next projects we will not use any components from the company "Analog Devices"....

Hi MatMaz ,

I apologize for the delay in support. I followed up and asked the responsible engineer to take a look into this.

While waiting, I checked the datasheet and looked into the registers affected before and after malfunction.

From what I read, 

The register 0x01 changed from 0x00 to 0x80 which shows there is an interrupt occurred in the LVDS receiver.



It seems this is causing the controller to stop.




Were you able to perform the recommended sample delay calibration before enabling surveillance mode or auto mode?



Once again, I apologize for the delay in response. I'll follow up and ask the product owner to take a look into this.

Best regards,
Peevee

Hi, i'm working in the same project with MatMaz.

Probably problem with stop working is solved, because we didn't notice this behavior again. Probably problem was with termination for LVDS lines. Can You confirm that all data, and data clock lines not need adding termination, but DAC_CLK need it in form described in datasheet?

Now we have another problem :) We get periodical spikes in output signal with freqency 1GHz, when DACCLK is 500MHz. Output signal is triangle, sine, or one value - allways we get this 1GHz spikes with voltage about 600mVpp.

I tried to manipulate with configuration, and just UPDEL set to max reduce spikes voltage from 0,6Vpp to 0,5Vpp, and reduced 3rd harmonics.

I tried to operate in manual mode (as described on datasheet page 42), but i still get FIFOSTAT odd(1-7) value, so i don't know i can "correct" it by PHOF. Enabling auto mode after it gives no effect.

I tried to operate LVDS controller in manual mode via SPI (page 41) and i can find MSD value (3), but when i'm trying to find
MHD value, CHECK bit never gets low. I tried to "be feel" set SD for example for 2, and try find MHD again - CHECK still didn't gets low. I think this can be some part of issue source, because as i understadn this parameters are strongly related with data and clock synchronization. When we reduce clocks 2x, spikes frequency reduces 2x too.

I tried to add RC low-pass filter on output but thats solution eats about 10dB from signal, but the used signal to spikes ratio goes higher about 10dB too.

Can you suggest something?

That our output signal (15M sine wave).

What is strange, we tried to sends stable immutable data value to DAC, and output signal still contains this spikes, oscilating around 0V, not around some DC off-set.

This probably excludes data/clock synchronization issue. In unsigned mode it didn't occurs (we get 0V on output), because data was out of range for this mode (i mean).

Hi Bob,

Please give us time while I coordinate with product owner to check your concern. 

Best regards,
Peevee

Hi, when i can expect some suggestions?
I'm sligtli suprised, by no valuable answers for about two months. Product exist on market above 10 years, so i think this problem performed in some cases, and solution should be partly know. I know that each case is different, but chip serving circuit isn't much expanded, so there no occurs hundreds of unique circuts.
We choosen Your DAC, cause offers good performance for our application, but i'm sligthly suprised by just one valuable answer for 2 months.

Hi, when i can expect some suggestions?
I'm sligtli suprised, by no valuable answers for about two months. Product exist on market above 10 years, so i think this problem performed in some cases, and solution should be partly know. I know that each case is different, but chip serving circuit isn't much expanded, so there no occurs hundreds of unique circuts.
We choosen Your DAC, cause offers good performance for our application, but i'm sligthly suprised by just one valuable answer for 2 months.

Hi Bob2000,

Thank you for your patience.

We are actively looking into the question you posted and will send an update as soon as we're done performing the required bench evaluation to replicate your setup and results.

Best regards,
Zaeefa

Hi Bob2000 ,

Our sincere apologies for the delay in providing a response to your concern.

Kindly check the following to help us troubleshoot the problem:

1. Output Circuitry. At which point of your output did you obtain the waveform? From the info you provided, second harmonic distortion seems to be present in the signal, which may have to do with the output load being imbalanced (refer to the DAC OUTPUT DISTORTION SOURCES section in page 51 of the datasheet). Moreover, your design appears to be using an amplifier at the output since the signal goes beyond AD9735's compliance range of +/- 1 V. Can you provide the updated schematic of your design so we can check your output circuitry? It would also be helpful if you could share the full output spectrum as well.
2. Clock Source. How is the clock signal being generated? Did you add a drive circuit to interface the clock input with the AD9735 (DACCLK) similar to the one in the datasheet (see DRIVING THE DACCLK INPUT section in page 50)? If you have an evaluation board, you can try following this quick start guide and see if the output shown in the guide can be achieved using the same clock source.
3. Register Values. What configurations did you use for the device? Can you provide us with the updated set of register values used for the AD9735?

To see an actual implementation of the datasheet recommendations mentioned above, the AD9735 evaluation board schematic (AD9735-DPG2-EBZ) can be seen in pages 57 to 61 of the datasheet or accessed through this link. Below scope captures show the output waveform and spectrum obtained from the DAC through the said evaluation board using the same configurations in your setup (single tone, 15-MHz output, 500-MHz clock/data rate) and following the quick start guide for the rest of the settings.

Thanks,
Zaeefa

HI, thanks for answer.

Below is my circut. DACCLK connection is made similar as on page 50 of datasheet - figure 90, and 92, what is not to seen on below schematic.

1. I get this signal on points indicated by geen arrows (differential probe). Interrupting signal path by remove T1, or capacitor next to him, has no significant impact on spikes. Spikes period is related with DACCLK frequency - when we incerase it two times, spikes period drops two times. Now i have no full spectrum, but this included in topic is comparable to Your spectrum, difference is that i do not have spike on ~500MHz, and usable sinal to spikes level difference is about 30-33dB (in my case about 28). I suggest You to make full scale sine.

2. DACCLK signal is connected as You suggested: page 50 of datasheet - figure 90, and 92. Its not made on schematic but in phisical device it is. Singal was generated by FPGA, and goes to LTC6952, and next to DAC, but now we connected it to LMK04906 to get 1GHz clk for DAC, but i didnt measure output signal jet. I have no evaluation board.

3. That is registers config:
REG / VALUE
0x00 0x20
0x01 0x00
0x02 0x02
0x03 0x00
0x04 0x00
0x05 0x00
0x06 0x00
0x07 0x00
0x08 0x40
0x0A 0x00
0x0B 0x00
0x0E 0xC0
0x0F 0xCA
0x11 0x00
0x12 0x00
0x13 0x00
0x14 0x00
0x15 0x00
0x16 0x00

4. Generaly that signal quality as You show on scope, and spectrum is max for this DAC? If yest, im curious what results will You get if You will made full scale test. Because we may be putting too much hope into it - i hope no.

Hi Bob2000,

Thank you for providing more info on your setup. Kindly refer to the screenshots below for the spectrum of the output from the DAC (obtained through the evaluation board at J2) configured with the settings described in your reply (at 20-mA full-scale). Looking at the first Nyquist zone (third figure), no spur with significantly high amplitude is present and an SFDR of ~86 dBc is measured, which is comparable to the performance illustrated in the datasheet (see Figure 41 in p. 24).

A waveform that closely resembles your output was also obtained by measuring at points A and B of the evaluation board using a differential probe. Note that both the spectrum and waveform were captured with balun T3 removed.

The values you used for the registers are mostly the DAC's default except for the RESET and SAUTO bits which are set to 1. These deviations should not introduce any kind of distortion to the signal; however, I suggest following the instructions stated in the datasheet on the correct assignment of these bits for proper manual operation (see the SYNC LOGIC AND CONTROLLER section in p. 42).

In summary, there appears to be no issue with your setup; the periodic spikes that are seen in the waveform appear to be distortion caused by the second clock harmonic and images which are typically present in the output of such a high-speed DAC. To eliminate these spike-like components, designing and using a reconstruction filter that can effectively remove/minimize the spurs without compromising the SNR of the signal at the output is highly recommended. Adding a balun (T3 in the eval board) to improve load balancing may also help reduce this distortion (see p. 51 of the datasheet).

Below figures show waveforms captured using a 4-GHz channel bandwidth versus 200 MHz measured at the same test points. Note the substantial reduction in spikes without noticeable change in the amplitude of the signal.

Hope this helps.

Regards,

Zaeefa