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AD9735 DAC stops working after some time

Category: Hardware

Hi, I have a problem with the operation of the AD9735 chip.

We have produced two custom PCBs using these chips. In both there is the same problem. The circuit after switching on works correctly, the signal generated is correct, the circuit reads the configuration, responds, for example, to PD mode, change of current(reg 2,3). However, after some time, usually about 20-40 minutes, the circuit stops working. The output data disappears. The clock is still present, data from the FPGA processor is sent, SPI communication works. The temperature of the chip , measured with a thermocouple-type probe, is about 40 degrees C.


reading registers during correct operation, reading registers after a malfunction:

DAC clocking signal: 500/600 MHz
If the problem occurs, the only solution is to temporarily cut off power to the DAC chip. Simply uploading the configuration, turning PD mode on and off, uploading the FPGA configuration again, does not resume the DAC operation.

Best regards,

  • Hi MM,

    Your query is acknowledged and will be responded by the product owner soon.

    Best regards,

  • Hello,
    it's been a month since I wrote a request for help. Until now, I haven't heard from anyone. Does Analog Devices provide any technical support for their products? Are users forced to solve all problems on their own?

    During testing I was able to verify that the converter has 3 possible modes of operation into which it enters after a power start:
    1. voltage level VPP A,
    2. voltage level VPP B,
    3. no output signal but with SPI communication operation. 

    All with the same input signal....

  • Another week has passed. I still haven't even received a suggestion to solve the problem. Does anyone on this forum deal with support? I understand that after paying for the ordered parts you have to cope on your own?

    If this is how it is supposed to look like then unfortunately but in the next projects we will not use any components from the company "Analog Devices"....

  • Hi  ,

    I apologize for the delay in support. I followed up and asked the responsible engineer to take a look into this.

    While waiting, I checked the datasheet and looked into the registers affected before and after malfunction.

    From what I read, 

    The register 0x01 changed from 0x00 to 0x80 which shows there is an interrupt occurred in the LVDS receiver.

    It seems this is causing the controller to stop.

    Were you able to perform the recommended sample delay calibration before enabling surveillance mode or auto mode?

    Once again, I apologize for the delay in response. I'll follow up and ask the product owner to take a look into this.

    Best regards,

  • Hi, i'm working in the same project with MatMaz.

    Probably problem with stop working is solved, because we didn't notice this behavior again. Probably problem was with termination for LVDS lines. Can You confirm that all data, and data clock lines not need adding termination, but DAC_CLK need it in form described in datasheet?

    Now we have another problem :) We get periodical spikes in output signal with freqency 1GHz, when DACCLK is 500MHz. Output signal is triangle, sine, or one value - allways we get this 1GHz spikes with voltage about 600mVpp.

    I tried to manipulate with configuration, and just UPDEL set to max reduce spikes voltage from 0,6Vpp to 0,5Vpp, and reduced 3rd harmonics.

    I tried to operate in manual mode (as described on datasheet page 42), but i still get FIFOSTAT odd(1-7) value, so i don't know i can "correct" it by PHOF. Enabling auto mode after it gives no effect.

    I tried to operate LVDS controller in manual mode via SPI (page 41) and i can find MSD value (3), but when i'm trying to find
    MHD value, CHECK bit never gets low. I tried to "be feel" set SD for example for 2, and try find MHD again - CHECK still didn't gets low. I think this can be some part of issue source, because as i understadn this parameters are strongly related with data and clock synchronization. When we reduce clocks 2x, spikes frequency reduces 2x too.

    I tried to add RC low-pass filter on output but thats solution eats about 10dB from signal, but the used signal to spikes ratio goes higher about 10dB too.

    Can you suggest something?

    That our output signal (15M sine wave).

  • What is strange, we tried to sends stable immutable data value to DAC, and output signal still contains this spikes, oscilating around 0V, not around some DC off-set.

    This probably excludes data/clock synchronization issue. In unsigned mode it didn't occurs (we get 0V on output), because data was out of range for this mode (i mean).

  • Hi Bob,

    Please give us time while I coordinate with product owner to check your concern. 

    Best regards,

  • Hi, when i can expect some suggestions?
    I'm sligtli suprised, by no valuable answers for about two months. Product exist on market above 10 years, so i think this problem performed in some cases, and solution should be partly know. I know that each case is different, but chip serving circuit isn't much expanded, so there no occurs hundreds of unique circuts.
    We choosen Your DAC, cause offers good performance for our application, but i'm sligthly suprised by just one valuable answer for 2 months.

  • Hi ,

    Thank you for your patience.

    We are actively looking into the question you posted and will send an update as soon as we're done performing the required bench evaluation to replicate your setup and results.

    Best regards,

  • Hi  ,

    Our sincere apologies for the delay in providing a response to your concern.

    Kindly check the following to help us troubleshoot the problem:

    1. Output Circuitry. At which point of your output did you obtain the waveform? From the info you provided, second harmonic distortion seems to be present in the signal, which may have to do with the output load being imbalanced (refer to the DAC OUTPUT DISTORTION SOURCES section in page 51 of the datasheet). Moreover, your design appears to be using an amplifier at the output since the signal goes beyond AD9735's compliance range of +/- 1 V. Can you provide the updated schematic of your design so we can check your output circuitry? It would also be helpful if you could share the full output spectrum as well.
    2. Clock Source. How is the clock signal being generated? Did you add a drive circuit to interface the clock input with the AD9735 (DACCLK) similar to the one in the datasheet (see DRIVING THE DACCLK INPUT section in page 50)? If you have an evaluation board, you can try following this quick start guide and see if the output shown in the guide can be achieved using the same clock source.
    3. Register Values. What configurations did you use for the device? Can you provide us with the updated set of register values used for the AD9735?

    To see an actual implementation of the datasheet recommendations mentioned above, the AD9735 evaluation board schematic (AD9735-DPG2-EBZ) can be seen in pages 57 to 61 of the datasheet or accessed through this link. Below scope captures show the output waveform and spectrum obtained from the DAC through the said evaluation board using the same configurations in your setup (single tone, 15-MHz output, 500-MHz clock/data rate) and following the quick start guide for the rest of the settings.