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AD9744 Output Problem

Category: Datasheet/Specs
Product Number: AD9744 -FMC-EBZ

Hi,

1) I would like to know at wich frequency we can clock the dac AD9744, because it isn't clear for me on the datasheet. How can we now it?

2)I see on page 5 in dynamic performance "Maximum Output Update Rate (fCLOCK)" a minimum value of 210 MSPS.
Does it mean that clock frequency must be higher than 210 MSPS (210 MHz) ? 

3) page 4 ,AC linearity: Spurious-Free Dynamic Range Within a Window and Spurious-Free Dynamic Range to Nyquist, what they different and why my signal have so much noise ?

4)  I want to do signal generator with this card , Is it suitable for this job? ( My expectation is Min 100 MHz output signal. )  

Top Replies

  • Hi  ,

    1. The AD9744 family has a sampling rate of up to 210 MSPS. You can use any sampling frequency within this range. Make sure the DAC clock has low jitter, high rise time and low phase noise…

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  • Hi  ,

    1. The AD9744 family has a sampling rate of up to 210 MSPS. You can use any sampling frequency within this range. Make sure the DAC clock has low jitter, high rise time and low phase noise to maximize converter performance. 

    2. The "Maximum Output Update Rate" with a "minimum value of 210 Msps" means that the user can apply a clock greater than 210Msps to the DAC Clock, but the performance won't be optimized.

    3. SFDR to Nyquist is the SFDR value at the 1st Nyquist zone (0 to Fs/2), while SFDR Within a Window specifies the highest SFDR value that's within the specified span and the desired output frequency. 

    4. The AD9744 can output a 100MHz signal, but we usually recommend getting a DAC with a sampling rate (Fclk) at least 4x the desired Fout. In your case, a minimum sampling rate of 400MSPS. Please check if AD9781 would suit your requirements. You could also check out other HSDAC selection from this link.

    Regards,

    Marco

Reply
  • Hi  ,

    1. The AD9744 family has a sampling rate of up to 210 MSPS. You can use any sampling frequency within this range. Make sure the DAC clock has low jitter, high rise time and low phase noise to maximize converter performance. 

    2. The "Maximum Output Update Rate" with a "minimum value of 210 Msps" means that the user can apply a clock greater than 210Msps to the DAC Clock, but the performance won't be optimized.

    3. SFDR to Nyquist is the SFDR value at the 1st Nyquist zone (0 to Fs/2), while SFDR Within a Window specifies the highest SFDR value that's within the specified span and the desired output frequency. 

    4. The AD9744 can output a 100MHz signal, but we usually recommend getting a DAC with a sampling rate (Fclk) at least 4x the desired Fout. In your case, a minimum sampling rate of 400MSPS. Please check if AD9781 would suit your requirements. You could also check out other HSDAC selection from this link.

    Regards,

    Marco

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