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A large timing skew between multiple LTC2000s synchronized

Category: Hardware
Product Number: LTC2000
My board uses four LTC2000s, with a PLL chip providing 2GHz sample clocks for the four DACs and an FPGA providing 500MHz data clock and data for the four DACs.  The PCB trace length of the sample clock, data clock and data, the DAC output between the four DACs is designed to be equal, and the diff is within 5mil. The actual time skew between the four sample clocks is about 20ps measured by an oscilloscop.
However, the synchronous skew of the four DACs output is sometimes large in actual test, the largest is about 300ps, and the skew of each board is different. The value of the register "SYNC_PS " has been adjusted according to the "Synchronizing Multiple LTC2000s in Dual-Port Mode" section in the LTC2000 datasheet, but does not seem useful for the skew of less than 1 sampling cycle (500ps here). I would like to ask what are the possible reasons for this large skew. And how much difference does the aperture delay of different DAC chips vary?
The simple block diagram of my board.
The synchronous skew of the four DACs output measured by an oscilloscop.
on Jul 31, 2023 8:25 PM in reply to guoxiaoyang

Hi  ,

Thanks for a great question, Overall, addressing synchronous skew issues can be challenging, and it often requires careful PCB design, signal integrity analysis, and possibly additional compensation techniques to minimize the effects of process and environmental 

  1. Temperature Variation: Temperature variations across the DAC chips can impact their performance, including output skew. The temperature gradient across the board or individual chips can lead to variations in propagation delays.

  2. Power Supply Noise: Noise on the power supply lines can cause variations in the DAC's behavior, affecting the output skew.

  3. Clock Jitter: Even though the sample clocks are designed to be synchronous, there might be slight jitter in the clocks, which can lead to skew in the DAC outputs.

  4. Signal Integrity: Signal integrity issues such as reflections, crosstalk, or impedance mismatches in the PCB traces can introduce timing differences in the signals, resulting in skew.

  5. Phase Mismatch in PLLs: The PLL that provides the 2GHz sample clocks might have slight phase mismatches between the different DACs, leading to skew in their outputs.

  6. Process Variation: Manufacturing process variations can lead to slight differences in the electrical characteristics of the DAC chips. These variations can affect the propagation delays and introduce skew in the output signals.

Regarding the aperture delay variation between different DAC chips (LTC2000s), The LTC2000 datasheet provides information on the typical aperture delay values of 300ps, for you to measure 300os skew which means that DAC did not even trigger?!! which leads me to believe its something else in the design ( like the 6 factors above) 

I will discuss this setup with our clocking group for any advice.  feel free to contact me directly for more details about your project since you seem to have a full operating system. the more details we get, the more we could help.



  • Hi Adam,

      Thanks for your reply. The typical aperture delay value of LTC2000 provided by datasheet is 3ns. And the skew of dac output we measured is large than 300ps in some channels.

      The PLL we use is LTC6952 which provide 2GHz sample clock to the four LTC2000s. LTC6952’s configuration is like this.


      We have confirmed that the output of LTC6952 is synchronous. And the time skew between the four sample clocks we measured is less than 20ps. There are some measurement results of 2GHz clock signal.

      Single-ended output waveform of the four clock signals


    Differential output waveform of two clock signals


      We've also did some other tests below.

    1. We reduced the sampling rate to 1GHz, the time skew of the four DACs outputis same as 2GHz.

    2. We use the pattern generator in LTC2000 to send sample data instead of DCKIP/N, DAP/N and DBP/N, however the time skew of the four DACs outputis no difference.

    3. We replaced one of the DACs with LTC2000A and found that the skew of this channel changed significantly.However there may have some difference between LTC2000 and LTC2000A.

      I think the main factors that affect the synchronous skew of multiple LTC2000s are the sample clock skew, the dac output PCB trace and the difference between dac chips. But it seems no problem. So I have no idea about this large skew. I’m looking forward to your suggestions.



  • FormerMember
    0 FormerMember on Aug 1, 2023 11:46 AM in reply to guoxiaoyang

    Hi Guoxuaoyang,

    Did you follow the procedure in the datasheet? "Measuring LVDS Input Timing Skew " on page 30, 31 and 32?



  • Hi Adam,

      I didn’t measure the LVDS input timing skew. I think it’s to measure the skew between data clock and data to ensure setup and hold margin of the incoming data. If the margin is not enough, the wave DAC output will be abnormal such as having glitch. I didn’t see such anomalies in the DAC output waveform. I think this issue may not be a main factor that affect the synchronous skew of multiple LTC2000s, cause I use the pattern generator in LTC2000 to send sample data instead of DCKIP/N, DAP/N and DBP/N but the time skew of the four DACs output is no difference.