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Regarding the channel interpolation issue with AD9172

Category: Software
Software Version: 1.13

 I am developing a product using the AD917x API driver provided by your company, and it works perfectly on my development board as long as the JESD mode does not involve channel interpolation. Modes 8, 18, and 3 work fine, but when using channel interpolation, such as mode 1, sometimes after writing the register configuration, I get the expected waveform and stable operation, while other times the oscilloscope shows a constant 0 after the write operation.Can you provide a reference example with channel interpolation and the lane count of 2 or more, If possible, it would be preferable to avoid using the channel NCO.It would be preferable if it is in C language code. If not available, a register configuration table would also be helpful. Thank you.

  • Hello, do you mean when you run ad917x_jesd_config_datapath() with the ch_intpl argument > 1 you periodically see no output? Are you following the recommended start up sequence in the datasheet, specifically table 53: JESD204B Mode Setup? There is also a jesd configuration flow chart on page 86 of the api specification document that may be useful. 

  • Hello, thank you for your response. I am not experiencing a periodic loss of output but rather random occurrences. After writing to the register, if the expected waveform output is present, the AD9172 operates normally until I reset it and write to it again. However, in the exact same program and board setup, there is no output after writing to the register (most of the time). Regarding the JESD mode configuration sequence you mentioned, I believe I am doing it correctly. There is a reference program in the official API provided by your company for initialization and parameter configuration. I made modifications based on that to meet the requirements of my project, My modifications only involve changing parameters and have not altered the sequence of the functions. and it works properly without using channel interpolation.

    There is another minor issue that I'm not sure if it's relevant. The data I read using the ad917x_jesd_get_link_status function shows that I haven't successfully established a link (all data is 0). However, when I capture the Sync and TReady signals using the FPGA's ILA (Integrated Logic Analyzer), it shows that the link has been established successfully and the link is stable. The Sync signal does not have any transitions. Since the chip is functioning properly, I have overlooked this minor issue.

  • Hello, 
    Are you referring to the main.c project in the no-os folder and adjusting the channel interpolation parameter (and/or jesd mode param) as below? If not, can you point me to the example program you are working from? I don't see anything in the AD917x_API-Rel1.1.1 package beyond the app_dac_init() example on pg 83 of the spec doc and accompanying flowcharts.

    I am not sure what is meant by "After writing to the register", which register do you mean? Are you updating the parameter and then rerunning a main program to reinitialize/reconfigure the whole chip, or are you making a separate call in some way?

  • Hello, thank you for your reply. The issue has been resolved. I made a foolish and basic mistake that caused this problem. Currently, the problem has been resolved.