AD9172 SerDes PLL unlocked at ~13G bitrate

Hello, when you say "I have tried use the divided DAC CLKin clocks 650 MHz, 325 MHz with multiply internally by DAC PLL but with no result" do you mean that you are only able to get the dac pll to lock with a clkin of 1.3GHz from the HMC, and it wont lock when the reference input from the HMC is lower? What is your dac output sample rate (Fdac) and your jesd mode? I can try to replicate your case on my setup.

Hello, kberry, thanks for your answer,

I mean that the DAC PLL locked at all DAC CLKin frequencies from HMC - 1300 MHz, 650 and 325 MHz but the SERDES PLL wont lock in all cases.

DAC input IQ-data sampled at 1300 MHz, used interpolation by 8 for obtaining 10,4 Gsps output sample rate. JESD mode is 8 (I have tried and mode 10), JESD bitrate 13 Gbps. DAC CLKin from HMC 1300 MHz.

What interesting - one DAC chip work well at 1300 MHz CLKin but dont work with little lower input frequency - I have find the gap from 1265 to 1285 MHz (SERDES PLL in not locked and JESD dont work). And the next chip dont work with the input DAC CLKin freq range 1270 - 1305 MHz.

"I can try to replicate your case on my setup"

It would be great!

Ion

The locking of the serdes pll should only depend on the dac clock, not the clkin value going to the dac pll, so it makes sense that if its not locking for one dac clock rate it wont lock regardless of the pll input clock used to produce that rate. But regardless I don't see any reason why it wouldn't lock with a 10.4GHz input to create output clocks for a 13gbps lane rate. I am using the eval board which has a 122.88Mhz crystal for HMC PLL1, so I can't get your exact rates using the HMC, but when I use a direct clock of 10.4GHz to the dac (bypass the dac pll) the serdes pll does lock for the 13gbps lane rate. So there shouldn't be an issue with the chip producing the serdes pll value. Do you have any way of sending 10.4Ghz directly to the clkin pins and bypassing the dac pll?

When you say the chips dont work with a certain dac clkin frequency range you mean the dac pll locks in those ranges but just that the serdes pll does not, right? So its not that those clkin frequencies are not working, its that the lane rate needed when using those frequencies with the rest of your parameters is near 13gbps, and the serdes pll seems like it wont lock around 13gbps, correct? Just want to isolate the issue at the serdes pll, and not at the dac pll or dac clkin pins.

Since the dac pll is locking there doesnt seem to be a signal integrity issue with the clkin pins, so the problem does appear to be with the chip, but the fact that its true with both chips and that I cannot replicate the issue is very strange... There shouldn't be a problem using this rate... 

Hi, kberry,

"When you say the chips dont work with a certain dac clkin frequency range you mean the dac pll locks in those ranges but just that the serdes pll does not, right?"

All right.

"Do you have any way of sending 10.4Ghz directly to the clkin pins and bypassing the dac pll?"

I haven't ability to send 10.4 GHz directly to DAC - the high frequency of onboard HMC's VCXOs limited to 3550 MHz, and external clock connection is not expected, but I have tried send to DAC clock 2,6 GHz and some lower frequencies and bypass DAC PLL (I know that the minimum input clock in bypass mode is 2,91 GHz) by writing registers: 0x095<= 0x01, 0x790<= 0xFF, 0x791<= 0x1F. Interpolation not used, DAC real data incoming from the FPGA at 2,6 GHz with JESD bitrate 13 Gbps. And I have seen the identic situation - DAC works but with gaps in bitrate frequencies.

Therefore I think that the cause is not DAC PLL. As a version - spurs of output HMC clock at this gap frequencies, but I haven't the phase noise analyzer to see it (

kberry, can you try to replicate my case at the next output frequencies of HMC on your board (with VCXO PLL1 122,88 Mhz), interpolation x8 is on:

1,29024 Ghz (VCXO=2,58048 Ghz: R2=2 with doubler, N2=21) -> JESD 12,9024 Gbps

1,281465 Ghz (2,56293 Ghz, R2=7, doubler, N2=73) -> JESD 12,81465 Gbps

1,26976 Ghz (2,53952, R2=3, doubler, N2=31) -> JESD 12,6976 Gbps

Thanks a lot!

ion

Hi, kberry,

"When you say the chips dont work with a certain dac clkin frequency range you mean the dac pll locks in those ranges but just that the serdes pll does not, right?"

All right.

"Do you have any way of sending 10.4Ghz directly to the clkin pins and bypassing the dac pll?"

I haven't ability to send 10.4 GHz directly to DAC - the high frequency of onboard HMC's VCXOs limited to 3550 MHz, and external clock connection is not expected, but I have tried send to DAC clock 2,6 GHz and some lower frequencies and bypass DAC PLL (I know that the minimum input clock in bypass mode is 2,91 GHz) by writing registers: 0x095<= 0x01, 0x790<= 0xFF, 0x791<= 0x1F. Interpolation not used, DAC real data incoming from the FPGA at 2,6 GHz with JESD bitrate 13 Gbps. And I have seen the identic situation - DAC works but with gaps in bitrate frequencies.

Therefore I think that the cause is not DAC PLL. As a version - spurs of output HMC clock at this gap frequencies, but I haven't the phase noise analyzer to see it (

kberry, can you try to replicate my case at the next output frequencies of HMC on your board (with VCXO PLL1 122,88 Mhz), interpolation x8 is on:

1,29024 Ghz (VCXO=2,58048 Ghz: R2=2 with doubler, N2=21) -> JESD 12,9024 Gbps

1,281465 Ghz (2,56293 Ghz, R2=7, doubler, N2=73) -> JESD 12,81465 Gbps

1,26976 Ghz (2,53952, R2=3, doubler, N2=31) -> JESD 12,6976 Gbps

Thanks a lot!

ion

Assumed answered.