dealing with AD9172 DAC at the my custom board I have meet with the absent of locking SerDes PLL (0x281 register) at bitrate range from 12,7 to 13,05 Gbps (first DAC chip) and from 12,65 to 12,85 Gb (second chip). This bitrates correspond required output DAC CLK frequencies 10,16-10,44 GHz and 10,12-10,28 GHz using interpolation by 8 with input IQ-data sample rate near 1,3 GHz. But the DAC PLL is locked in all frequencies and DLL locked also.
DAC CLKin 1,3 GHz is generated with HMC7044 in dual-loop mode with TCXO ref 25MHz and VCXO Crystek 100MHz, internal PLLs are locked, as I have seen the clock is clear.I have tried use the divided DAC CLKin clocks 650 MHz, 325 MHz with multiply internally by DAC PLL but with no result.
The powering of DAC made based ADP1763 with independent power lines AVDD/DVDD/SVDD with additional passive filtering, the noise level seems by scope so fine.
DAC initialization sequence standard, using AD driver.
I have tried different sample rates and JESD bitrates from 12,5 to 15,5 Gbps but such gap in SerDes lock I have find only near 13 Gbps bitrate. Whats the problem may be with the SerDes locking, is any idea?