I have the AD9176-FMC-EBC + ZCU102 eval boards working in the mode 4 reference design. I would like to increase the default sample rate of 11.8 Gsps as I have a signal close to nyquist.
This is the default clocking configuration:
pll2-out: 2,949,120,000 (24x clkin)
DAC_CLK: 368,640,000 (/8)
DAC_SYSREF: 5,760,000 (/512)
FPGA_CLK: 368,640,000 (/8)
FPGA_SYSREF: 5,760,000 (/512)
dac-rate: 11,796,480,000 (32x DAC_CLK)
I tried changing the pll2-out to be 25x rather than 24x the reference (just as an example of something easy I thought should work)
These should be the new frequencies:
pll2-out: 3,072,000,000 (25x clkin)
DAC_CLK: 384,000,000 (/8)
DAC_SYSREF: 6,000,000 (/512)
FPGA_CLK: 384,000,000 (/8)
FPGA_SYSREF: 6,000,000 (/512)
dac-rate: 12,288,000,000 (32x DAC_CLK)
I made the following 2 device tree changes to increase the pll2 frequency and set the new dac rate.
adi,pll2-output-frequency = <3072000000>;
adi,dac-rate-khz = <12288000>; /* 12.288 GSPS */
When I turn on the board I see the HMC7044 locks at the higher frequency because the red LED goes out but the AD9176 fails to initialize as shown in the following dmesg. All frequencies are within spec so I'm not sure what the issue is.
[ 3.635467] ad9172 spi1.1: ad917x DAC Chip ID: 4
[ 3.640078] ad9172 spi1.1: ad917x DAC Product ID: 9176
[ 3.645205] ad9172 spi1.1: ad917x DAC Product Grade: 0
[ 3.650335] ad9172 spi1.1: ad917x DAC Product Revision: 7
[ 3.655725] ad9172 spi1.1: ad917x Revision: 1.1.1
[ 3.660425] ad9172 spi1.1: CLK Input rate 384000000
[ 3.665503] ad9172 spi1.1: ad917x_set_dac_clk failed (-22)
[ 3.670987] ad9172 spi1.1: Failed to setup device
[ 3.675801] ad9172: probe of spi1.1 failed with error -22
I also tried setting pll2 to 24.5x the input with the same result.
Are there any other changes that must be made such as to the FPGA image in order to change the sample rate?
When we go to build our own board we will likely want a 126 MHz reference and then keep the default 24x multiplier. Are there any considerations I should be aware of for that?